5 #ifndef V8_ARM_CONSTANTS_ARM_H_ 6 #define V8_ARM_CONSTANTS_ARM_H_ 10 #include "src/base/logging.h" 11 #include "src/base/macros.h" 12 #include "src/boxed-float.h" 13 #include "src/globals.h" 14 #include "src/utils.h" 17 #if defined(__arm__) && !defined(__ARM_EABI__) 18 #error ARM EABI support is required. 26 const int kConstantPoolMarkerMask = 0xfff000f0;
27 const int kConstantPoolMarker = 0xe7f000f0;
28 const int kConstantPoolLengthMaxMask = 0xffff;
29 inline int EncodeConstantPoolLength(
int length) {
30 DCHECK((length & kConstantPoolLengthMaxMask) == length);
31 return ((length & 0xfff0) << 4) | (length & 0xf);
33 inline int DecodeConstantPoolLength(
int instr) {
34 DCHECK_EQ(instr & kConstantPoolMarkerMask, kConstantPoolMarker);
35 return ((instr >> 4) & 0xfff0) | (instr & 0xf);
39 constexpr
int kNumRegisters = 16;
40 constexpr
int kRegSizeInBitsLog2 = 5;
43 constexpr
int kNumVFPSingleRegisters = 32;
44 constexpr
int kNumVFPDoubleRegisters = 32;
45 constexpr
int kNumVFPRegisters =
46 kNumVFPSingleRegisters + kNumVFPDoubleRegisters;
49 constexpr
int kPCRegister = 15;
50 constexpr
int kNoRegister = -1;
54 constexpr
int kLdrMaxReachBits = 12;
55 constexpr
int kVldrMaxReachBits = 10;
61 constexpr
int kRootRegisterBias = 4095;
95 kSpecialCondition = 15 << 28,
96 kNumberOfConditions = 16,
104 inline Condition NegateCondition(Condition cond) {
106 return static_cast<Condition
>(cond ^ ne);
117 typedef int32_t Instr;
143 enum MiscInstructionsBits74 {
192 kCondMask = 15 << 28,
193 kALUMask = 0x6f << 21,
195 kCoprocessorMask = 15 << 8,
196 kOpCodeMask = 15 << 21,
197 kImm24Mask = (1 << 24) - 1,
198 kImm16Mask = (1 << 16) - 1,
199 kImm8Mask = (1 << 8) - 1,
200 kOff12Mask = (1 << 12) - 1,
201 kOff8Mask = (1 << 8) - 1
254 enum SRegisterField {
255 CPSR_c = CPSR | 1 << 16,
256 CPSR_x = CPSR | 1 << 17,
257 CPSR_s = CPSR | 1 << 18,
258 CPSR_f = CPSR | 1 << 19,
259 SPSR_c = SPSR | 1 << 16,
260 SPSR_x = SPSR | 1 << 17,
261 SPSR_s = SPSR | 1 << 18,
262 SPSR_f = SPSR | 1 << 19
266 typedef uint32_t SRegisterFieldMask;
272 Offset = (8|4|0) << 21,
273 PreIndex = (8|4|1) << 21,
274 PostIndex = (0|4|0) << 21,
275 NegOffset = (8|0|0) << 21,
276 NegPreIndex = (8|0|1) << 21,
277 NegPostIndex = (0|0|0) << 21
288 da_w = (0|0|1) << 21,
289 ia_w = (0|4|1) << 21,
290 db_w = (8|0|1) << 21,
291 ib_w = (8|4|1) << 21,
294 da_x = (0|0|0) << 21,
295 ia_x = (0|4|0) << 21,
296 db_x = (8|0|0) << 21,
297 ib_x = (8|4|0) << 21,
299 kBlockAddrModeMask = (8|4|1) << 21
310 enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 };
323 inline int NeonU(NeonDataType dt) {
return static_cast<int>(dt) >> 2; }
324 inline int NeonSz(NeonDataType dt) {
return static_cast<int>(dt) & 0x3; }
327 inline NeonDataType NeonSizeToDataType(NeonSize size) {
328 DCHECK_NE(Neon64, size);
329 return static_cast<NeonDataType
>(size);
332 inline NeonSize NeonDataTypeToSize(NeonDataType dt) {
333 return static_cast<NeonSize
>(NeonSz(dt));
350 enum SoftwareInterruptCodes {
352 kCallRtRedirected = 0x10,
358 const uint32_t kStopCodeMask = kStopCode - 1;
359 const uint32_t kMaxStopCode = kStopCode - 1;
360 const int32_t kDefaultStopCode = -1;
364 enum VFPRegPrecision {
365 kSinglePrecision = 0,
366 kDoublePrecision = 1,
367 kSimd128Precision = 2
371 enum VFPConversionMode {
373 kDefaultRoundToZero = 1
378 const uint32_t kVFPExceptionMask = 0xf;
379 const uint32_t kVFPInvalidOpExceptionBit = 1 << 0;
380 const uint32_t kVFPOverflowExceptionBit = 1 << 2;
381 const uint32_t kVFPUnderflowExceptionBit = 1 << 3;
382 const uint32_t kVFPInexactExceptionBit = 1 << 4;
383 const uint32_t kVFPFlushToZeroMask = 1 << 24;
384 const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25;
386 const uint32_t kVFPNConditionFlagBit = 1 << 31;
387 const uint32_t kVFPZConditionFlagBit = 1 << 30;
388 const uint32_t kVFPCConditionFlagBit = 1 << 29;
389 const uint32_t kVFPVConditionFlagBit = 1 << 28;
393 enum VFPRoundingMode {
400 kRoundToNearest = RN,
401 kRoundToPlusInf = RP,
402 kRoundToMinusInf = RM,
406 const uint32_t kVFPRoundingModeMask = 3 << 22;
408 enum CheckForInexactConversion {
409 kCheckForInexactConversion,
410 kDontCheckForInexactConversion
419 enum Hint { no_hint };
422 inline Hint NegateHint(Hint ignored) {
return no_hint; }
442 constexpr uint8_t kInstrSize = 4;
443 constexpr uint8_t kInstrSizeLog2 = 2;
449 static constexpr
int kPcLoadDelta = 8;
453 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ 454 static inline return_type Name(Instr instr) { \ 455 char* temp = reinterpret_cast<char*>(&instr); \ 456 return reinterpret_cast<Instruction*>(temp)->Name(); \ 459 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) 462 inline Instr InstructionBits()
const {
463 return *
reinterpret_cast<const Instr*
>(
this);
467 inline void SetInstructionBits(Instr value) {
468 *
reinterpret_cast<Instr*
>(
this) = value;
473 inline int Bit(
int nr)
const {
474 return (InstructionBits() >> nr) & 1;
479 inline int Bits(
int hi,
int lo)
const {
480 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
484 inline int BitField(
int hi,
int lo)
const {
485 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo);
492 static inline int Bit(Instr instr,
int nr) {
493 return (instr >> nr) & 1;
498 static inline int Bits(Instr instr,
int hi,
int lo) {
499 return (instr >> lo) & ((2 << (hi - lo)) - 1);
503 static inline int BitField(Instr instr,
int hi,
int lo) {
504 return instr & (((2 << (hi - lo)) - 1) << lo);
521 inline int ConditionValue()
const {
return Bits(31, 28); }
522 inline Condition ConditionField()
const {
523 return static_cast<Condition
>(
BitField(31, 28));
525 DECLARE_STATIC_TYPED_ACCESSOR(
int, ConditionValue);
526 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField);
528 inline int TypeValue()
const {
return Bits(27, 25); }
529 inline int SpecialValue()
const {
return Bits(27, 23); }
531 inline int RnValue()
const {
return Bits(19, 16); }
532 DECLARE_STATIC_ACCESSOR(RnValue);
533 inline int RdValue()
const {
return Bits(15, 12); }
534 DECLARE_STATIC_ACCESSOR(RdValue);
536 inline int CoprocessorValue()
const {
return Bits(11, 8); }
539 inline int VnValue()
const {
return Bits(19, 16); }
540 inline int VmValue()
const {
return Bits(3, 0); }
541 inline int VdValue()
const {
return Bits(15, 12); }
542 inline int NValue()
const {
return Bit(7); }
543 inline int MValue()
const {
return Bit(5); }
544 inline int DValue()
const {
return Bit(22); }
545 inline int RtValue()
const {
return Bits(15, 12); }
546 inline int PValue()
const {
return Bit(24); }
547 inline int UValue()
const {
return Bit(23); }
548 inline int Opc1Value()
const {
return (Bit(23) << 2) | Bits(21, 20); }
549 inline int Opc2Value()
const {
return Bits(19, 16); }
550 inline int Opc3Value()
const {
return Bits(7, 6); }
551 inline int SzValue()
const {
return Bit(8); }
552 inline int VLValue()
const {
return Bit(20); }
553 inline int VCValue()
const {
return Bit(8); }
554 inline int VAValue()
const {
return Bits(23, 21); }
555 inline int VBValue()
const {
return Bits(6, 5); }
556 inline int VFPNRegValue(VFPRegPrecision pre) {
557 return VFPGlueRegValue(pre, 16, 7);
559 inline int VFPMRegValue(VFPRegPrecision pre) {
560 return VFPGlueRegValue(pre, 0, 5);
562 inline int VFPDRegValue(VFPRegPrecision pre) {
563 return VFPGlueRegValue(pre, 12, 22);
567 inline int OpcodeValue()
const {
568 return static_cast<Opcode
>(Bits(24, 21));
570 inline Opcode OpcodeField()
const {
571 return static_cast<Opcode
>(
BitField(24, 21));
573 inline int SValue()
const {
return Bit(20); }
575 inline int RmValue()
const {
return Bits(3, 0); }
576 DECLARE_STATIC_ACCESSOR(RmValue);
577 inline int ShiftValue()
const {
return static_cast<ShiftOp
>(Bits(6, 5)); }
578 inline ShiftOp ShiftField()
const {
579 return static_cast<ShiftOp
>(
BitField(6, 5));
581 inline int RegShiftValue()
const {
return Bit(4); }
582 inline int RsValue()
const {
return Bits(11, 8); }
583 inline int ShiftAmountValue()
const {
return Bits(11, 7); }
585 inline int RotateValue()
const {
return Bits(11, 8); }
586 DECLARE_STATIC_ACCESSOR(RotateValue);
587 inline int Immed8Value()
const {
return Bits(7, 0); }
588 DECLARE_STATIC_ACCESSOR(Immed8Value);
589 inline int Immed4Value()
const {
return Bits(19, 16); }
590 inline int ImmedMovwMovtValue()
const {
591 return Immed4Value() << 12 | Offset12Value(); }
592 DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue);
595 inline int PUValue()
const {
return Bits(24, 23); }
596 inline int PUField()
const {
return BitField(24, 23); }
597 inline int BValue()
const {
return Bit(22); }
598 inline int WValue()
const {
return Bit(21); }
599 inline int LValue()
const {
return Bit(20); }
602 inline int Offset12Value()
const {
return Bits(11, 0); }
604 inline int RlistValue()
const {
return Bits(15, 0); }
606 inline int SignValue()
const {
return Bit(6); }
607 inline int HValue()
const {
return Bit(5); }
608 inline int ImmedHValue()
const {
return Bits(11, 8); }
609 inline int ImmedLValue()
const {
return Bits(3, 0); }
612 inline int LinkValue()
const {
return Bit(24); }
613 inline int SImmed24Value()
const {
614 return signed_bitextract_32(23, 0, InstructionBits());
617 bool IsBranch() {
return Bit(27) == 1 && Bit(25) == 1; }
619 int GetBranchOffset() {
621 return SImmed24Value() * kInstrSize;
624 void SetBranchOffset(int32_t branch_offset) {
626 DCHECK_EQ(branch_offset % kInstrSize, 0);
627 int32_t new_imm24 = branch_offset / kInstrSize;
628 CHECK(is_int24(new_imm24));
629 SetInstructionBits((InstructionBits() & ~(kImm24Mask)) |
630 (new_imm24 & kImm24Mask));
634 inline SoftwareInterruptCodes SvcValue()
const {
635 return static_cast<SoftwareInterruptCodes
>(Bits(23, 0));
640 inline bool IsSpecialType0()
const {
return (Bit(7) == 1) && (Bit(4) == 1); }
643 inline bool IsMiscType0()
const {
return (Bit(24) == 1)
646 && ((Bit(7) == 0)); }
649 inline bool IsNopLikeType1()
const {
return Bits(24, 8) == 0x120F0; }
652 inline bool IsStop()
const {
653 return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode);
657 inline bool HasS()
const {
return SValue() == 1; }
658 inline bool HasB()
const {
return BValue() == 1; }
659 inline bool HasW()
const {
return WValue() == 1; }
660 inline bool HasL()
const {
return LValue() == 1; }
661 inline bool HasU()
const {
return UValue() == 1; }
662 inline bool HasSign()
const {
return SignValue() == 1; }
663 inline bool HasH()
const {
return HValue() == 1; }
664 inline bool HasLink()
const {
return LinkValue() == 1; }
667 Float64 DoubleImmedVmov()
const;
683 inline int VFPGlueRegValue(VFPRegPrecision pre,
int four_bit,
int one_bit) {
684 if (pre == kSinglePrecision) {
685 return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
687 int reg_num = (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
688 if (pre == kDoublePrecision) {
691 DCHECK_EQ(kSimd128Precision, pre);
692 DCHECK_EQ(reg_num & 1, 0);
706 static const char*
Name(
int reg);
709 static int Number(
const char* name);
717 static const char* names_[kNumRegisters];
725 static const char*
Name(
int reg,
bool is_double);
730 static int Number(
const char* name,
bool* is_double);
733 static const char* names_[kNumVFPRegisters];
737 constexpr
size_t kMaxPCRelativeCodeRangeInMB = 32;
742 #endif // V8_ARM_CONSTANTS_ARM_H_