V8 API Reference, 7.2.502.16 (for Deno 0.2.4)
constants-arm.h
1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #ifndef V8_ARM_CONSTANTS_ARM_H_
6 #define V8_ARM_CONSTANTS_ARM_H_
7 
8 #include <stdint.h>
9 
10 #include "src/base/logging.h"
11 #include "src/base/macros.h"
12 #include "src/boxed-float.h"
13 #include "src/globals.h"
14 #include "src/utils.h"
15 
16 // ARM EABI is required.
17 #if defined(__arm__) && !defined(__ARM_EABI__)
18 #error ARM EABI support is required.
19 #endif
20 
21 namespace v8 {
22 namespace internal {
23 
24 // Constant pool marker.
25 // Use UDF, the permanently undefined instruction.
26 const int kConstantPoolMarkerMask = 0xfff000f0;
27 const int kConstantPoolMarker = 0xe7f000f0;
28 const int kConstantPoolLengthMaxMask = 0xffff;
29 inline int EncodeConstantPoolLength(int length) {
30  DCHECK((length & kConstantPoolLengthMaxMask) == length);
31  return ((length & 0xfff0) << 4) | (length & 0xf);
32 }
33 inline int DecodeConstantPoolLength(int instr) {
34  DCHECK_EQ(instr & kConstantPoolMarkerMask, kConstantPoolMarker);
35  return ((instr >> 4) & 0xfff0) | (instr & 0xf);
36 }
37 
38 // Number of registers in normal ARM mode.
39 constexpr int kNumRegisters = 16;
40 constexpr int kRegSizeInBitsLog2 = 5;
41 
42 // VFP support.
43 constexpr int kNumVFPSingleRegisters = 32;
44 constexpr int kNumVFPDoubleRegisters = 32;
45 constexpr int kNumVFPRegisters =
46  kNumVFPSingleRegisters + kNumVFPDoubleRegisters;
47 
48 // PC is register 15.
49 constexpr int kPCRegister = 15;
50 constexpr int kNoRegister = -1;
51 
52 // Used in embedded constant pool builder - max reach in bits for
53 // various load instructions (unsigned)
54 constexpr int kLdrMaxReachBits = 12;
55 constexpr int kVldrMaxReachBits = 10;
56 
57 // Actual value of root register is offset from the root array's start
58 // to take advantage of negative displacement values. Loads allow a uint12
59 // value with a separate sign bit (range [-4095, +4095]), so the first root
60 // is still addressable with a single load instruction.
61 constexpr int kRootRegisterBias = 4095;
62 
63 // -----------------------------------------------------------------------------
64 // Conditions.
65 
66 // Defines constants and accessor classes to assemble, disassemble and
67 // simulate ARM instructions.
68 //
69 // Section references in the code refer to the "ARM Architecture Reference
70 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
71 //
72 // Constants for specific fields are defined in their respective named enums.
73 // General constants are in an anonymous enum in class Instr.
74 
75 // Values for the condition field as defined in section A3.2
76 enum Condition {
77  kNoCondition = -1,
78 
79  eq = 0 << 28, // Z set Equal.
80  ne = 1 << 28, // Z clear Not equal.
81  cs = 2 << 28, // C set Unsigned higher or same.
82  cc = 3 << 28, // C clear Unsigned lower.
83  mi = 4 << 28, // N set Negative.
84  pl = 5 << 28, // N clear Positive or zero.
85  vs = 6 << 28, // V set Overflow.
86  vc = 7 << 28, // V clear No overflow.
87  hi = 8 << 28, // C set, Z clear Unsigned higher.
88  ls = 9 << 28, // C clear or Z set Unsigned lower or same.
89  ge = 10 << 28, // N == V Greater or equal.
90  lt = 11 << 28, // N != V Less than.
91  gt = 12 << 28, // Z clear, N == V Greater than.
92  le = 13 << 28, // Z set or N != V Less then or equal
93  al = 14 << 28, // Always.
94 
95  kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1).
96  kNumberOfConditions = 16,
97 
98  // Aliases.
99  hs = cs, // C set Unsigned higher or same.
100  lo = cc // C clear Unsigned lower.
101 };
102 
103 
104 inline Condition NegateCondition(Condition cond) {
105  DCHECK(cond != al);
106  return static_cast<Condition>(cond ^ ne);
107 }
108 
109 
110 // -----------------------------------------------------------------------------
111 // Instructions encoding.
112 
113 // Instr is merely used by the Assembler to distinguish 32bit integers
114 // representing instructions from usual 32 bit values.
115 // Instruction objects are pointers to 32bit values, and provide methods to
116 // access the various ISA fields.
117 typedef int32_t Instr;
118 
119 
120 // Opcodes for Data-processing instructions (instructions with a type 0 and 1)
121 // as defined in section A3.4
122 enum Opcode {
123  AND = 0 << 21, // Logical AND.
124  EOR = 1 << 21, // Logical Exclusive OR.
125  SUB = 2 << 21, // Subtract.
126  RSB = 3 << 21, // Reverse Subtract.
127  ADD = 4 << 21, // Add.
128  ADC = 5 << 21, // Add with Carry.
129  SBC = 6 << 21, // Subtract with Carry.
130  RSC = 7 << 21, // Reverse Subtract with Carry.
131  TST = 8 << 21, // Test.
132  TEQ = 9 << 21, // Test Equivalence.
133  CMP = 10 << 21, // Compare.
134  CMN = 11 << 21, // Compare Negated.
135  ORR = 12 << 21, // Logical (inclusive) OR.
136  MOV = 13 << 21, // Move.
137  BIC = 14 << 21, // Bit Clear.
138  MVN = 15 << 21 // Move Not.
139 };
140 
141 
142 // The bits for bit 7-4 for some type 0 miscellaneous instructions.
143 enum MiscInstructionsBits74 {
144  // With bits 22-21 01.
145  BX = 1 << 4,
146  BXJ = 2 << 4,
147  BLX = 3 << 4,
148  BKPT = 7 << 4,
149 
150  // With bits 22-21 11.
151  CLZ = 1 << 4
152 };
153 
154 
155 // Instruction encoding bits and masks.
156 enum {
157  H = 1 << 5, // Halfword (or byte).
158  S6 = 1 << 6, // Signed (or unsigned).
159  L = 1 << 20, // Load (or store).
160  S = 1 << 20, // Set condition code (or leave unchanged).
161  W = 1 << 21, // Writeback base register (or leave unchanged).
162  A = 1 << 21, // Accumulate in multiply instruction (or not).
163  B = 1 << 22, // Unsigned byte (or word).
164  N = 1 << 22, // Long (or short).
165  U = 1 << 23, // Positive (or negative) offset/index.
166  P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing).
167  I = 1 << 25, // Immediate shifter operand (or not).
168  B0 = 1 << 0,
169  B4 = 1 << 4,
170  B5 = 1 << 5,
171  B6 = 1 << 6,
172  B7 = 1 << 7,
173  B8 = 1 << 8,
174  B9 = 1 << 9,
175  B10 = 1 << 10,
176  B12 = 1 << 12,
177  B16 = 1 << 16,
178  B17 = 1 << 17,
179  B18 = 1 << 18,
180  B19 = 1 << 19,
181  B20 = 1 << 20,
182  B21 = 1 << 21,
183  B22 = 1 << 22,
184  B23 = 1 << 23,
185  B24 = 1 << 24,
186  B25 = 1 << 25,
187  B26 = 1 << 26,
188  B27 = 1 << 27,
189  B28 = 1 << 28,
190 
191  // Instruction bit masks.
192  kCondMask = 15 << 28,
193  kALUMask = 0x6f << 21,
194  kRdMask = 15 << 12, // In str instruction.
195  kCoprocessorMask = 15 << 8,
196  kOpCodeMask = 15 << 21, // In data-processing instructions.
197  kImm24Mask = (1 << 24) - 1,
198  kImm16Mask = (1 << 16) - 1,
199  kImm8Mask = (1 << 8) - 1,
200  kOff12Mask = (1 << 12) - 1,
201  kOff8Mask = (1 << 8) - 1
202 };
203 
204 enum BarrierOption {
205  OSHLD = 0x1,
206  OSHST = 0x2,
207  OSH = 0x3,
208  NSHLD = 0x5,
209  NSHST = 0x6,
210  NSH = 0x7,
211  ISHLD = 0x9,
212  ISHST = 0xa,
213  ISH = 0xb,
214  LD = 0xd,
215  ST = 0xe,
216  SY = 0xf,
217 };
218 
219 
220 // -----------------------------------------------------------------------------
221 // Addressing modes and instruction variants.
222 
223 // Condition code updating mode.
224 enum SBit {
225  SetCC = 1 << 20, // Set condition code.
226  LeaveCC = 0 << 20 // Leave condition code unchanged.
227 };
228 
229 
230 // Status register selection.
231 enum SRegister {
232  CPSR = 0 << 22,
233  SPSR = 1 << 22
234 };
235 
236 
237 // Shifter types for Data-processing operands as defined in section A5.1.2.
238 enum ShiftOp {
239  LSL = 0 << 5, // Logical shift left.
240  LSR = 1 << 5, // Logical shift right.
241  ASR = 2 << 5, // Arithmetic shift right.
242  ROR = 3 << 5, // Rotate right.
243 
244  // RRX is encoded as ROR with shift_imm == 0.
245  // Use a special code to make the distinction. The RRX ShiftOp is only used
246  // as an argument, and will never actually be encoded. The Assembler will
247  // detect it and emit the correct ROR shift operand with shift_imm == 0.
248  RRX = -1,
249  kNumberOfShifts = 4
250 };
251 
252 
253 // Status register fields.
254 enum SRegisterField {
255  CPSR_c = CPSR | 1 << 16,
256  CPSR_x = CPSR | 1 << 17,
257  CPSR_s = CPSR | 1 << 18,
258  CPSR_f = CPSR | 1 << 19,
259  SPSR_c = SPSR | 1 << 16,
260  SPSR_x = SPSR | 1 << 17,
261  SPSR_s = SPSR | 1 << 18,
262  SPSR_f = SPSR | 1 << 19
263 };
264 
265 // Status register field mask (or'ed SRegisterField enum values).
266 typedef uint32_t SRegisterFieldMask;
267 
268 
269 // Memory operand addressing mode.
270 enum AddrMode {
271  // Bit encoding P U W.
272  Offset = (8|4|0) << 21, // Offset (without writeback to base).
273  PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback.
274  PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback.
275  NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base).
276  NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback.
277  NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback.
278 };
279 
280 
281 // Load/store multiple addressing mode.
282 enum BlockAddrMode {
283  // Bit encoding P U W .
284  da = (0|0|0) << 21, // Decrement after.
285  ia = (0|4|0) << 21, // Increment after.
286  db = (8|0|0) << 21, // Decrement before.
287  ib = (8|4|0) << 21, // Increment before.
288  da_w = (0|0|1) << 21, // Decrement after with writeback to base.
289  ia_w = (0|4|1) << 21, // Increment after with writeback to base.
290  db_w = (8|0|1) << 21, // Decrement before with writeback to base.
291  ib_w = (8|4|1) << 21, // Increment before with writeback to base.
292 
293  // Alias modes for comparison when writeback does not matter.
294  da_x = (0|0|0) << 21, // Decrement after.
295  ia_x = (0|4|0) << 21, // Increment after.
296  db_x = (8|0|0) << 21, // Decrement before.
297  ib_x = (8|4|0) << 21, // Increment before.
298 
299  kBlockAddrModeMask = (8|4|1) << 21
300 };
301 
302 
303 // Coprocessor load/store operand size.
304 enum LFlag {
305  Long = 1 << 22, // Long load/store coprocessor.
306  Short = 0 << 22 // Short load/store coprocessor.
307 };
308 
309 // Neon sizes.
310 enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 };
311 
312 // NEON data type
313 enum NeonDataType {
314  NeonS8 = 0,
315  NeonS16 = 1,
316  NeonS32 = 2,
317  // Gap to make it easier to extract U and size.
318  NeonU8 = 4,
319  NeonU16 = 5,
320  NeonU32 = 6
321 };
322 
323 inline int NeonU(NeonDataType dt) { return static_cast<int>(dt) >> 2; }
324 inline int NeonSz(NeonDataType dt) { return static_cast<int>(dt) & 0x3; }
325 
326 // Convert sizes to data types (U bit is clear).
327 inline NeonDataType NeonSizeToDataType(NeonSize size) {
328  DCHECK_NE(Neon64, size);
329  return static_cast<NeonDataType>(size);
330 }
331 
332 inline NeonSize NeonDataTypeToSize(NeonDataType dt) {
333  return static_cast<NeonSize>(NeonSz(dt));
334 }
335 
336 enum NeonListType {
337  nlt_1 = 0x7,
338  nlt_2 = 0xA,
339  nlt_3 = 0x6,
340  nlt_4 = 0x2
341 };
342 
343 // -----------------------------------------------------------------------------
344 // Supervisor Call (svc) specific support.
345 
346 // Special Software Interrupt codes when used in the presence of the ARM
347 // simulator.
348 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
349 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
350 enum SoftwareInterruptCodes {
351  // transition to C code
352  kCallRtRedirected = 0x10,
353  // break point
354  kBreakpoint = 0x20,
355  // stop
356  kStopCode = 1 << 23
357 };
358 const uint32_t kStopCodeMask = kStopCode - 1;
359 const uint32_t kMaxStopCode = kStopCode - 1;
360 const int32_t kDefaultStopCode = -1;
361 
362 
363 // Type of VFP register. Determines register encoding.
364 enum VFPRegPrecision {
365  kSinglePrecision = 0,
366  kDoublePrecision = 1,
367  kSimd128Precision = 2
368 };
369 
370 // VFP FPSCR constants.
371 enum VFPConversionMode {
372  kFPSCRRounding = 0,
373  kDefaultRoundToZero = 1
374 };
375 
376 // This mask does not include the "inexact" or "input denormal" cumulative
377 // exceptions flags, because we usually don't want to check for it.
378 const uint32_t kVFPExceptionMask = 0xf;
379 const uint32_t kVFPInvalidOpExceptionBit = 1 << 0;
380 const uint32_t kVFPOverflowExceptionBit = 1 << 2;
381 const uint32_t kVFPUnderflowExceptionBit = 1 << 3;
382 const uint32_t kVFPInexactExceptionBit = 1 << 4;
383 const uint32_t kVFPFlushToZeroMask = 1 << 24;
384 const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25;
385 
386 const uint32_t kVFPNConditionFlagBit = 1 << 31;
387 const uint32_t kVFPZConditionFlagBit = 1 << 30;
388 const uint32_t kVFPCConditionFlagBit = 1 << 29;
389 const uint32_t kVFPVConditionFlagBit = 1 << 28;
390 
391 
392 // VFP rounding modes. See ARM DDI 0406B Page A2-29.
393 enum VFPRoundingMode {
394  RN = 0 << 22, // Round to Nearest.
395  RP = 1 << 22, // Round towards Plus Infinity.
396  RM = 2 << 22, // Round towards Minus Infinity.
397  RZ = 3 << 22, // Round towards zero.
398 
399  // Aliases.
400  kRoundToNearest = RN,
401  kRoundToPlusInf = RP,
402  kRoundToMinusInf = RM,
403  kRoundToZero = RZ
404 };
405 
406 const uint32_t kVFPRoundingModeMask = 3 << 22;
407 
408 enum CheckForInexactConversion {
409  kCheckForInexactConversion,
410  kDontCheckForInexactConversion
411 };
412 
413 // -----------------------------------------------------------------------------
414 // Hints.
415 
416 // Branch hints are not used on the ARM. They are defined so that they can
417 // appear in shared function signatures, but will be ignored in ARM
418 // implementations.
419 enum Hint { no_hint };
420 
421 // Hints are not used on the arm. Negating is trivial.
422 inline Hint NegateHint(Hint ignored) { return no_hint; }
423 
424 
425 // -----------------------------------------------------------------------------
426 // Instruction abstraction.
427 
428 // The class Instruction enables access to individual fields defined in the ARM
429 // architecture instruction set encoding as described in figure A3-1.
430 // Note that the Assembler uses typedef int32_t Instr.
431 //
432 // Example: Test whether the instruction at ptr does set the condition code
433 // bits.
434 //
435 // bool InstructionSetsConditionCodes(byte* ptr) {
436 // Instruction* instr = Instruction::At(ptr);
437 // int type = instr->TypeValue();
438 // return ((type == 0) || (type == 1)) && instr->HasS();
439 // }
440 //
441 
442 constexpr uint8_t kInstrSize = 4;
443 constexpr uint8_t kInstrSizeLog2 = 2;
444 
445 class Instruction {
446  public:
447  // Difference between address of current opcode and value read from pc
448  // register.
449  static constexpr int kPcLoadDelta = 8;
450 
451 // Helper macro to define static accessors.
452 // We use the cast to char* trick to bypass the strict anti-aliasing rules.
453 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \
454  static inline return_type Name(Instr instr) { \
455  char* temp = reinterpret_cast<char*>(&instr); \
456  return reinterpret_cast<Instruction*>(temp)->Name(); \
457  }
458 
459 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name)
460 
461  // Get the raw instruction bits.
462  inline Instr InstructionBits() const {
463  return *reinterpret_cast<const Instr*>(this);
464  }
465 
466  // Set the raw instruction bits to value.
467  inline void SetInstructionBits(Instr value) {
468  *reinterpret_cast<Instr*>(this) = value;
469  }
470 
471  // Extract a single bit from the instruction bits and return it as bit 0 in
472  // the result.
473  inline int Bit(int nr) const {
474  return (InstructionBits() >> nr) & 1;
475  }
476 
477  // Extract a bit field <hi:lo> from the instruction bits and return it in the
478  // least-significant bits of the result.
479  inline int Bits(int hi, int lo) const {
480  return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
481  }
482 
483  // Read a bit field <hi:lo>, leaving its position unchanged in the result.
484  inline int BitField(int hi, int lo) const {
485  return InstructionBits() & (((2 << (hi - lo)) - 1) << lo);
486  }
487 
488  // Static support.
489 
490  // Extract a single bit from the instruction bits and return it as bit 0 in
491  // the result.
492  static inline int Bit(Instr instr, int nr) {
493  return (instr >> nr) & 1;
494  }
495 
496  // Extract a bit field <hi:lo> from the instruction bits and return it in the
497  // least-significant bits of the result.
498  static inline int Bits(Instr instr, int hi, int lo) {
499  return (instr >> lo) & ((2 << (hi - lo)) - 1);
500  }
501 
502  // Read a bit field <hi:lo>, leaving its position unchanged in the result.
503  static inline int BitField(Instr instr, int hi, int lo) {
504  return instr & (((2 << (hi - lo)) - 1) << lo);
505  }
506 
507  // Accessors for the different named fields used in the ARM encoding.
508  // The naming of these accessor corresponds to figure A3-1.
509  //
510  // Two kind of accessors are declared:
511  // - <Name>Field() will return the raw field, i.e. the field's bits at their
512  // original place in the instruction encoding.
513  // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
514  // 0xC0810002 ConditionField(instr) will return 0xC0000000.
515  // - <Name>Value() will return the field value, shifted back to bit 0.
516  // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
517  // 0xC0810002 ConditionField(instr) will return 0xC.
518 
519 
520  // Generally applicable fields
521  inline int ConditionValue() const { return Bits(31, 28); }
522  inline Condition ConditionField() const {
523  return static_cast<Condition>(BitField(31, 28));
524  }
525  DECLARE_STATIC_TYPED_ACCESSOR(int, ConditionValue);
526  DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField);
527 
528  inline int TypeValue() const { return Bits(27, 25); }
529  inline int SpecialValue() const { return Bits(27, 23); }
530 
531  inline int RnValue() const { return Bits(19, 16); }
532  DECLARE_STATIC_ACCESSOR(RnValue);
533  inline int RdValue() const { return Bits(15, 12); }
534  DECLARE_STATIC_ACCESSOR(RdValue);
535 
536  inline int CoprocessorValue() const { return Bits(11, 8); }
537  // Support for VFP.
538  // Vn(19-16) | Vd(15-12) | Vm(3-0)
539  inline int VnValue() const { return Bits(19, 16); }
540  inline int VmValue() const { return Bits(3, 0); }
541  inline int VdValue() const { return Bits(15, 12); }
542  inline int NValue() const { return Bit(7); }
543  inline int MValue() const { return Bit(5); }
544  inline int DValue() const { return Bit(22); }
545  inline int RtValue() const { return Bits(15, 12); }
546  inline int PValue() const { return Bit(24); }
547  inline int UValue() const { return Bit(23); }
548  inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); }
549  inline int Opc2Value() const { return Bits(19, 16); }
550  inline int Opc3Value() const { return Bits(7, 6); }
551  inline int SzValue() const { return Bit(8); }
552  inline int VLValue() const { return Bit(20); }
553  inline int VCValue() const { return Bit(8); }
554  inline int VAValue() const { return Bits(23, 21); }
555  inline int VBValue() const { return Bits(6, 5); }
556  inline int VFPNRegValue(VFPRegPrecision pre) {
557  return VFPGlueRegValue(pre, 16, 7);
558  }
559  inline int VFPMRegValue(VFPRegPrecision pre) {
560  return VFPGlueRegValue(pre, 0, 5);
561  }
562  inline int VFPDRegValue(VFPRegPrecision pre) {
563  return VFPGlueRegValue(pre, 12, 22);
564  }
565 
566  // Fields used in Data processing instructions
567  inline int OpcodeValue() const {
568  return static_cast<Opcode>(Bits(24, 21));
569  }
570  inline Opcode OpcodeField() const {
571  return static_cast<Opcode>(BitField(24, 21));
572  }
573  inline int SValue() const { return Bit(20); }
574  // with register
575  inline int RmValue() const { return Bits(3, 0); }
576  DECLARE_STATIC_ACCESSOR(RmValue);
577  inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
578  inline ShiftOp ShiftField() const {
579  return static_cast<ShiftOp>(BitField(6, 5));
580  }
581  inline int RegShiftValue() const { return Bit(4); }
582  inline int RsValue() const { return Bits(11, 8); }
583  inline int ShiftAmountValue() const { return Bits(11, 7); }
584  // with immediate
585  inline int RotateValue() const { return Bits(11, 8); }
586  DECLARE_STATIC_ACCESSOR(RotateValue);
587  inline int Immed8Value() const { return Bits(7, 0); }
588  DECLARE_STATIC_ACCESSOR(Immed8Value);
589  inline int Immed4Value() const { return Bits(19, 16); }
590  inline int ImmedMovwMovtValue() const {
591  return Immed4Value() << 12 | Offset12Value(); }
592  DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue);
593 
594  // Fields used in Load/Store instructions
595  inline int PUValue() const { return Bits(24, 23); }
596  inline int PUField() const { return BitField(24, 23); }
597  inline int BValue() const { return Bit(22); }
598  inline int WValue() const { return Bit(21); }
599  inline int LValue() const { return Bit(20); }
600  // with register uses same fields as Data processing instructions above
601  // with immediate
602  inline int Offset12Value() const { return Bits(11, 0); }
603  // multiple
604  inline int RlistValue() const { return Bits(15, 0); }
605  // extra loads and stores
606  inline int SignValue() const { return Bit(6); }
607  inline int HValue() const { return Bit(5); }
608  inline int ImmedHValue() const { return Bits(11, 8); }
609  inline int ImmedLValue() const { return Bits(3, 0); }
610 
611  // Fields used in Branch instructions
612  inline int LinkValue() const { return Bit(24); }
613  inline int SImmed24Value() const {
614  return signed_bitextract_32(23, 0, InstructionBits());
615  }
616 
617  bool IsBranch() { return Bit(27) == 1 && Bit(25) == 1; }
618 
619  int GetBranchOffset() {
620  DCHECK(IsBranch());
621  return SImmed24Value() * kInstrSize;
622  }
623 
624  void SetBranchOffset(int32_t branch_offset) {
625  DCHECK(IsBranch());
626  DCHECK_EQ(branch_offset % kInstrSize, 0);
627  int32_t new_imm24 = branch_offset / kInstrSize;
628  CHECK(is_int24(new_imm24));
629  SetInstructionBits((InstructionBits() & ~(kImm24Mask)) |
630  (new_imm24 & kImm24Mask));
631  }
632 
633  // Fields used in Software interrupt instructions
634  inline SoftwareInterruptCodes SvcValue() const {
635  return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
636  }
637 
638  // Test for special encodings of type 0 instructions (extra loads and stores,
639  // as well as multiplications).
640  inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); }
641 
642  // Test for miscellaneous instructions encodings of type 0 instructions.
643  inline bool IsMiscType0() const { return (Bit(24) == 1)
644  && (Bit(23) == 0)
645  && (Bit(20) == 0)
646  && ((Bit(7) == 0)); }
647 
648  // Test for nop-like instructions which fall under type 1.
649  inline bool IsNopLikeType1() const { return Bits(24, 8) == 0x120F0; }
650 
651  // Test for a stop instruction.
652  inline bool IsStop() const {
653  return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode);
654  }
655 
656  // Special accessors that test for existence of a value.
657  inline bool HasS() const { return SValue() == 1; }
658  inline bool HasB() const { return BValue() == 1; }
659  inline bool HasW() const { return WValue() == 1; }
660  inline bool HasL() const { return LValue() == 1; }
661  inline bool HasU() const { return UValue() == 1; }
662  inline bool HasSign() const { return SignValue() == 1; }
663  inline bool HasH() const { return HValue() == 1; }
664  inline bool HasLink() const { return LinkValue() == 1; }
665 
666  // Decode the double immediate from a vmov instruction.
667  Float64 DoubleImmedVmov() const;
668 
669  // Instructions are read of out a code stream. The only way to get a
670  // reference to an instruction is to convert a pointer. There is no way
671  // to allocate or create instances of class Instruction.
672  // Use the At(pc) function to create references to Instruction.
673  static Instruction* At(Address pc) {
674  return reinterpret_cast<Instruction*>(pc);
675  }
676 
677 
678  private:
679  // Join split register codes, depending on register precision.
680  // four_bit is the position of the least-significant bit of the four
681  // bit specifier. one_bit is the position of the additional single bit
682  // specifier.
683  inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) {
684  if (pre == kSinglePrecision) {
685  return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
686  } else {
687  int reg_num = (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
688  if (pre == kDoublePrecision) {
689  return reg_num;
690  }
691  DCHECK_EQ(kSimd128Precision, pre);
692  DCHECK_EQ(reg_num & 1, 0);
693  return reg_num / 2;
694  }
695  }
696 
697  // We need to prevent the creation of instances of class Instruction.
698  DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
699 };
700 
701 
702 // Helper functions for converting between register numbers and names.
703 class Registers {
704  public:
705  // Return the name of the register.
706  static const char* Name(int reg);
707 
708  // Lookup the register number for the name provided.
709  static int Number(const char* name);
710 
711  struct RegisterAlias {
712  int reg;
713  const char* name;
714  };
715 
716  private:
717  static const char* names_[kNumRegisters];
718  static const RegisterAlias aliases_[];
719 };
720 
721 // Helper functions for converting between VFP register numbers and names.
723  public:
724  // Return the name of the register.
725  static const char* Name(int reg, bool is_double);
726 
727  // Lookup the register number for the name provided.
728  // Set flag pointed by is_double to true if register
729  // is double-precision.
730  static int Number(const char* name, bool* is_double);
731 
732  private:
733  static const char* names_[kNumVFPRegisters];
734 };
735 
736 // Relative jumps on ARM can address ±32 MB.
737 constexpr size_t kMaxPCRelativeCodeRangeInMB = 32;
738 
739 } // namespace internal
740 } // namespace v8
741 
742 #endif // V8_ARM_CONSTANTS_ARM_H_
Definition: libplatform.h:13