V8 API Reference, 7.2.502.16 (for Deno 0.2.4)
macro-assembler-mips64.h
1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #ifndef INCLUDED_FROM_MACRO_ASSEMBLER_H
6 #error This header must be included via macro-assembler.h
7 #endif
8 
9 #ifndef V8_MIPS64_MACRO_ASSEMBLER_MIPS64_H_
10 #define V8_MIPS64_MACRO_ASSEMBLER_MIPS64_H_
11 
12 #include "src/assembler.h"
13 #include "src/globals.h"
14 #include "src/mips64/assembler-mips64.h"
15 
16 namespace v8 {
17 namespace internal {
18 
19 // Give alias names to registers for calling conventions.
20 constexpr Register kReturnRegister0 = v0;
21 constexpr Register kReturnRegister1 = v1;
22 constexpr Register kReturnRegister2 = a0;
23 constexpr Register kJSFunctionRegister = a1;
24 constexpr Register kContextRegister = s7;
25 constexpr Register kAllocateSizeRegister = a0;
26 constexpr Register kSpeculationPoisonRegister = a7;
27 constexpr Register kInterpreterAccumulatorRegister = v0;
28 constexpr Register kInterpreterBytecodeOffsetRegister = t0;
29 constexpr Register kInterpreterBytecodeArrayRegister = t1;
30 constexpr Register kInterpreterDispatchTableRegister = t2;
31 
32 constexpr Register kJavaScriptCallArgCountRegister = a0;
33 constexpr Register kJavaScriptCallCodeStartRegister = a2;
34 constexpr Register kJavaScriptCallTargetRegister = kJSFunctionRegister;
35 constexpr Register kJavaScriptCallNewTargetRegister = a3;
36 constexpr Register kJavaScriptCallExtraArg1Register = a2;
37 
38 constexpr Register kOffHeapTrampolineRegister = at;
39 constexpr Register kRuntimeCallFunctionRegister = a1;
40 constexpr Register kRuntimeCallArgCountRegister = a0;
41 constexpr Register kRuntimeCallArgvRegister = a2;
42 constexpr Register kWasmInstanceRegister = a0;
43 constexpr Register kWasmCompileLazyFuncIndexRegister = t0;
44 
45 // Forward declarations.
46 enum class AbortReason : uint8_t;
47 
48 // Reserved Register Usage Summary.
49 //
50 // Registers t8, t9, and at are reserved for use by the MacroAssembler.
51 //
52 // The programmer should know that the MacroAssembler may clobber these three,
53 // but won't touch other registers except in special cases.
54 //
55 // Per the MIPS ABI, register t9 must be used for indirect function call
56 // via 'jalr t9' or 'jr t9' instructions. This is relied upon by gcc when
57 // trying to update gp register for position-independent-code. Whenever
58 // MIPS generated code calls C code, it must be via t9 register.
59 
60 
61 // Flags used for LeaveExitFrame function.
62 enum LeaveExitFrameMode {
63  EMIT_RETURN = true,
64  NO_EMIT_RETURN = false
65 };
66 
67 // Allow programmer to use Branch Delay Slot of Branches, Jumps, Calls.
68 enum BranchDelaySlot {
69  USE_DELAY_SLOT,
70  PROTECT
71 };
72 
73 // Flags used for the li macro-assembler function.
74 enum LiFlags {
75  // If the constant value can be represented in just 16 bits, then
76  // optimize the li to use a single instruction, rather than lui/ori/dsll
77  // sequence. A number of other optimizations that emits less than
78  // maximum number of instructions exists.
79  OPTIMIZE_SIZE = 0,
80  // Always use 6 instructions (lui/ori/dsll sequence) for release 2 or 4
81  // instructions for release 6 (lui/ori/dahi/dati), even if the constant
82  // could be loaded with just one, so that this value is patchable later.
83  CONSTANT_SIZE = 1,
84  // For address loads only 4 instruction are required. Used to mark
85  // constant load that will be used as address without relocation
86  // information. It ensures predictable code size, so specific sites
87  // in code are patchable.
88  ADDRESS_LOAD = 2
89 };
90 
91 enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET };
92 enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK };
93 enum RAStatus { kRAHasNotBeenSaved, kRAHasBeenSaved };
94 
95 Register GetRegisterThatIsNotOneOf(Register reg1,
96  Register reg2 = no_reg,
97  Register reg3 = no_reg,
98  Register reg4 = no_reg,
99  Register reg5 = no_reg,
100  Register reg6 = no_reg);
101 
102 // -----------------------------------------------------------------------------
103 // Static helper functions.
104 
105 #if defined(V8_TARGET_LITTLE_ENDIAN)
106 #define SmiWordOffset(offset) (offset + kPointerSize / 2)
107 #else
108 #define SmiWordOffset(offset) offset
109 #endif
110 
111 
112 inline MemOperand ContextMemOperand(Register context, int index) {
113  return MemOperand(context, Context::SlotOffset(index));
114 }
115 
116 
117 inline MemOperand NativeContextMemOperand() {
118  return ContextMemOperand(cp, Context::NATIVE_CONTEXT_INDEX);
119 }
120 
121 
122 // Generate a MemOperand for loading a field from an object.
123 inline MemOperand FieldMemOperand(Register object, int offset) {
124  return MemOperand(object, offset - kHeapObjectTag);
125 }
126 
127 
128 // Generate a MemOperand for storing arguments 5..N on the stack
129 // when calling CallCFunction().
130 // TODO(plind): Currently ONLY used for O32. Should be fixed for
131 // n64, and used in RegExp code, and other places
132 // with more than 8 arguments.
133 inline MemOperand CFunctionArgumentOperand(int index) {
134  DCHECK_GT(index, kCArgSlotCount);
135  // Argument 5 takes the slot just past the four Arg-slots.
136  int offset = (index - 5) * kPointerSize + kCArgsSlotsSize;
137  return MemOperand(sp, offset);
138 }
139 
140 class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
141  public:
142  TurboAssembler(const AssemblerOptions& options, void* buffer, int buffer_size)
143  : TurboAssemblerBase(options, buffer, buffer_size) {}
144 
145  TurboAssembler(Isolate* isolate, const AssemblerOptions& options,
146  void* buffer, int buffer_size,
147  CodeObjectRequired create_code_object)
148  : TurboAssemblerBase(isolate, options, buffer, buffer_size,
149  create_code_object) {}
150 
151  // Activation support.
152  void EnterFrame(StackFrame::Type type);
153  void EnterFrame(StackFrame::Type type, bool load_constant_pool_pointer_reg) {
154  // Out-of-line constant pool not implemented on mips.
155  UNREACHABLE();
156  }
157  void LeaveFrame(StackFrame::Type type);
158 
159  // Generates function and stub prologue code.
160  void StubPrologue(StackFrame::Type type);
161  void Prologue();
162 
163  void InitializeRootRegister() {
164  ExternalReference isolate_root = ExternalReference::isolate_root(isolate());
165  li(kRootRegister, Operand(isolate_root));
166  }
167 
168  // Jump unconditionally to given label.
169  // We NEED a nop in the branch delay slot, as it used by v8, for example in
170  // CodeGenerator::ProcessDeferred().
171  // Currently the branch delay slot is filled by the MacroAssembler.
172  // Use rather b(Label) for code generation.
173  void jmp(Label* L) { Branch(L); }
174 
175  // -------------------------------------------------------------------------
176  // Debugging.
177 
178  // Calls Abort(msg) if the condition cc is not satisfied.
179  // Use --debug_code to enable.
180  void Assert(Condition cc, AbortReason reason, Register rs, Operand rt);
181 
182  // Like Assert(), but always enabled.
183  void Check(Condition cc, AbortReason reason, Register rs, Operand rt);
184 
185  // Print a message to stdout and abort execution.
186  void Abort(AbortReason msg);
187 
188  inline bool AllowThisStubCall(CodeStub* stub);
189 
190  // Arguments macros.
191 #define COND_TYPED_ARGS Condition cond, Register r1, const Operand& r2
192 #define COND_ARGS cond, r1, r2
193 
194  // Cases when relocation is not needed.
195 #define DECLARE_NORELOC_PROTOTYPE(Name, target_type) \
196  void Name(target_type target, BranchDelaySlot bd = PROTECT); \
197  inline void Name(BranchDelaySlot bd, target_type target) { \
198  Name(target, bd); \
199  } \
200  void Name(target_type target, \
201  COND_TYPED_ARGS, \
202  BranchDelaySlot bd = PROTECT); \
203  inline void Name(BranchDelaySlot bd, \
204  target_type target, \
205  COND_TYPED_ARGS) { \
206  Name(target, COND_ARGS, bd); \
207  }
208 
209 #define DECLARE_BRANCH_PROTOTYPES(Name) \
210  DECLARE_NORELOC_PROTOTYPE(Name, Label*) \
211  DECLARE_NORELOC_PROTOTYPE(Name, int32_t)
212 
213  DECLARE_BRANCH_PROTOTYPES(Branch)
214  DECLARE_BRANCH_PROTOTYPES(BranchAndLink)
215  DECLARE_BRANCH_PROTOTYPES(BranchShort)
216 
217 #undef DECLARE_BRANCH_PROTOTYPES
218 #undef COND_TYPED_ARGS
219 #undef COND_ARGS
220 
221  // Floating point branches
222  void CompareF32(FPUCondition cc, FPURegister cmp1, FPURegister cmp2) {
223  CompareF(S, cc, cmp1, cmp2);
224  }
225 
226  void CompareIsNanF32(FPURegister cmp1, FPURegister cmp2) {
227  CompareIsNanF(S, cmp1, cmp2);
228  }
229 
230  void CompareF64(FPUCondition cc, FPURegister cmp1, FPURegister cmp2) {
231  CompareF(D, cc, cmp1, cmp2);
232  }
233 
234  void CompareIsNanF64(FPURegister cmp1, FPURegister cmp2) {
235  CompareIsNanF(D, cmp1, cmp2);
236  }
237 
238  void BranchTrueShortF(Label* target, BranchDelaySlot bd = PROTECT);
239  void BranchFalseShortF(Label* target, BranchDelaySlot bd = PROTECT);
240 
241  void BranchTrueF(Label* target, BranchDelaySlot bd = PROTECT);
242  void BranchFalseF(Label* target, BranchDelaySlot bd = PROTECT);
243 
244  // MSA branches
245  void BranchMSA(Label* target, MSABranchDF df, MSABranchCondition cond,
246  MSARegister wt, BranchDelaySlot bd = PROTECT);
247 
248  void Branch(Label* L, Condition cond, Register rs, RootIndex index,
249  BranchDelaySlot bdslot = PROTECT);
250 
251  static int InstrCountForLi64Bit(int64_t value);
252  inline void LiLower32BitHelper(Register rd, Operand j);
253  void li_optimized(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE);
254  // Load int32 in the rd register.
255  void li(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE);
256  inline void li(Register rd, int64_t j, LiFlags mode = OPTIMIZE_SIZE) {
257  li(rd, Operand(j), mode);
258  }
259  // inline void li(Register rd, int32_t j, LiFlags mode = OPTIMIZE_SIZE) {
260  // li(rd, Operand(static_cast<int64_t>(j)), mode);
261  // }
262  void li(Register dst, Handle<HeapObject> value, LiFlags mode = OPTIMIZE_SIZE);
263  void li(Register dst, ExternalReference value, LiFlags mode = OPTIMIZE_SIZE);
264  void li(Register dst, const StringConstantBase* string,
265  LiFlags mode = OPTIMIZE_SIZE);
266 
267  void LoadFromConstantsTable(Register destination,
268  int constant_index) override;
269  void LoadRootRegisterOffset(Register destination, intptr_t offset) override;
270  void LoadRootRelative(Register destination, int32_t offset) override;
271 
272 // Jump, Call, and Ret pseudo instructions implementing inter-working.
273 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \
274  const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
275 
276  void Jump(Register target, COND_ARGS);
277  void Jump(intptr_t target, RelocInfo::Mode rmode, COND_ARGS);
278  void Jump(Address target, RelocInfo::Mode rmode, COND_ARGS);
279  void Jump(Handle<Code> code, RelocInfo::Mode rmode, COND_ARGS);
280  void Call(Register target, COND_ARGS);
281  void Call(Address target, RelocInfo::Mode rmode, COND_ARGS);
282  void Call(Handle<Code> code,
283  RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
284  COND_ARGS);
285  void Call(Label* target);
286 
287  void CallForDeoptimization(Address target, int deopt_id,
288  RelocInfo::Mode rmode) {
289  USE(deopt_id);
290  Call(target, rmode);
291  }
292 
293  void Ret(COND_ARGS);
294  inline void Ret(BranchDelaySlot bd, Condition cond = al,
295  Register rs = zero_reg, const Operand& rt = Operand(zero_reg)) {
296  Ret(cond, rs, rt, bd);
297  }
298 
299  // Emit code to discard a non-negative number of pointer-sized elements
300  // from the stack, clobbering only the sp register.
301  void Drop(int count,
302  Condition cond = cc_always,
303  Register reg = no_reg,
304  const Operand& op = Operand(no_reg));
305 
306  // Trivial case of DropAndRet that utilizes the delay slot and only emits
307  // 2 instructions.
308  void DropAndRet(int drop);
309 
310  void DropAndRet(int drop,
311  Condition cond,
312  Register reg,
313  const Operand& op);
314 
315  void Ld(Register rd, const MemOperand& rs);
316  void Sd(Register rd, const MemOperand& rs);
317 
318  void push(Register src) {
319  Daddu(sp, sp, Operand(-kPointerSize));
320  Sd(src, MemOperand(sp, 0));
321  }
322  void Push(Register src) { push(src); }
323  void Push(Handle<HeapObject> handle);
324  void Push(Smi smi);
325 
326  // Push two registers. Pushes leftmost register first (to highest address).
327  void Push(Register src1, Register src2) {
328  Dsubu(sp, sp, Operand(2 * kPointerSize));
329  Sd(src1, MemOperand(sp, 1 * kPointerSize));
330  Sd(src2, MemOperand(sp, 0 * kPointerSize));
331  }
332 
333  // Push three registers. Pushes leftmost register first (to highest address).
334  void Push(Register src1, Register src2, Register src3) {
335  Dsubu(sp, sp, Operand(3 * kPointerSize));
336  Sd(src1, MemOperand(sp, 2 * kPointerSize));
337  Sd(src2, MemOperand(sp, 1 * kPointerSize));
338  Sd(src3, MemOperand(sp, 0 * kPointerSize));
339  }
340 
341  // Push four registers. Pushes leftmost register first (to highest address).
342  void Push(Register src1, Register src2, Register src3, Register src4) {
343  Dsubu(sp, sp, Operand(4 * kPointerSize));
344  Sd(src1, MemOperand(sp, 3 * kPointerSize));
345  Sd(src2, MemOperand(sp, 2 * kPointerSize));
346  Sd(src3, MemOperand(sp, 1 * kPointerSize));
347  Sd(src4, MemOperand(sp, 0 * kPointerSize));
348  }
349 
350  // Push five registers. Pushes leftmost register first (to highest address).
351  void Push(Register src1, Register src2, Register src3, Register src4,
352  Register src5) {
353  Dsubu(sp, sp, Operand(5 * kPointerSize));
354  Sd(src1, MemOperand(sp, 4 * kPointerSize));
355  Sd(src2, MemOperand(sp, 3 * kPointerSize));
356  Sd(src3, MemOperand(sp, 2 * kPointerSize));
357  Sd(src4, MemOperand(sp, 1 * kPointerSize));
358  Sd(src5, MemOperand(sp, 0 * kPointerSize));
359  }
360 
361  void Push(Register src, Condition cond, Register tst1, Register tst2) {
362  // Since we don't have conditional execution we use a Branch.
363  Branch(3, cond, tst1, Operand(tst2));
364  Dsubu(sp, sp, Operand(kPointerSize));
365  Sd(src, MemOperand(sp, 0));
366  }
367 
368  void SaveRegisters(RegList registers);
369  void RestoreRegisters(RegList registers);
370 
371  void CallRecordWriteStub(Register object, Register address,
372  RememberedSetAction remembered_set_action,
373  SaveFPRegsMode fp_mode);
374  void CallRecordWriteStub(Register object, Register address,
375  RememberedSetAction remembered_set_action,
376  SaveFPRegsMode fp_mode, Address wasm_target);
377 
378  // Push multiple registers on the stack.
379  // Registers are saved in numerical order, with higher numbered registers
380  // saved in higher memory addresses.
381  void MultiPush(RegList regs);
382  void MultiPushFPU(RegList regs);
383 
384  // Calculate how much stack space (in bytes) are required to store caller
385  // registers excluding those specified in the arguments.
386  int RequiredStackSizeForCallerSaved(SaveFPRegsMode fp_mode,
387  Register exclusion1 = no_reg,
388  Register exclusion2 = no_reg,
389  Register exclusion3 = no_reg) const;
390 
391  // Push caller saved registers on the stack, and return the number of bytes
392  // stack pointer is adjusted.
393  int PushCallerSaved(SaveFPRegsMode fp_mode, Register exclusion1 = no_reg,
394  Register exclusion2 = no_reg,
395  Register exclusion3 = no_reg);
396  // Restore caller saved registers from the stack, and return the number of
397  // bytes stack pointer is adjusted.
398  int PopCallerSaved(SaveFPRegsMode fp_mode, Register exclusion1 = no_reg,
399  Register exclusion2 = no_reg,
400  Register exclusion3 = no_reg);
401 
402  void pop(Register dst) {
403  Ld(dst, MemOperand(sp, 0));
404  Daddu(sp, sp, Operand(kPointerSize));
405  }
406  void Pop(Register dst) { pop(dst); }
407 
408  // Pop two registers. Pops rightmost register first (from lower address).
409  void Pop(Register src1, Register src2) {
410  DCHECK(src1 != src2);
411  Ld(src2, MemOperand(sp, 0 * kPointerSize));
412  Ld(src1, MemOperand(sp, 1 * kPointerSize));
413  Daddu(sp, sp, 2 * kPointerSize);
414  }
415 
416  // Pop three registers. Pops rightmost register first (from lower address).
417  void Pop(Register src1, Register src2, Register src3) {
418  Ld(src3, MemOperand(sp, 0 * kPointerSize));
419  Ld(src2, MemOperand(sp, 1 * kPointerSize));
420  Ld(src1, MemOperand(sp, 2 * kPointerSize));
421  Daddu(sp, sp, 3 * kPointerSize);
422  }
423 
424  void Pop(uint32_t count = 1) { Daddu(sp, sp, Operand(count * kPointerSize)); }
425 
426  // Pops multiple values from the stack and load them in the
427  // registers specified in regs. Pop order is the opposite as in MultiPush.
428  void MultiPop(RegList regs);
429  void MultiPopFPU(RegList regs);
430 
431 #define DEFINE_INSTRUCTION(instr) \
432  void instr(Register rd, Register rs, const Operand& rt); \
433  void instr(Register rd, Register rs, Register rt) { \
434  instr(rd, rs, Operand(rt)); \
435  } \
436  void instr(Register rs, Register rt, int32_t j) { instr(rs, rt, Operand(j)); }
437 
438 #define DEFINE_INSTRUCTION2(instr) \
439  void instr(Register rs, const Operand& rt); \
440  void instr(Register rs, Register rt) { instr(rs, Operand(rt)); } \
441  void instr(Register rs, int32_t j) { instr(rs, Operand(j)); }
442 
443  DEFINE_INSTRUCTION(Addu);
444  DEFINE_INSTRUCTION(Daddu);
445  DEFINE_INSTRUCTION(Div);
446  DEFINE_INSTRUCTION(Divu);
447  DEFINE_INSTRUCTION(Ddivu);
448  DEFINE_INSTRUCTION(Mod);
449  DEFINE_INSTRUCTION(Modu);
450  DEFINE_INSTRUCTION(Ddiv);
451  DEFINE_INSTRUCTION(Subu);
452  DEFINE_INSTRUCTION(Dsubu);
453  DEFINE_INSTRUCTION(Dmod);
454  DEFINE_INSTRUCTION(Dmodu);
455  DEFINE_INSTRUCTION(Mul);
456  DEFINE_INSTRUCTION(Mulh);
457  DEFINE_INSTRUCTION(Mulhu);
458  DEFINE_INSTRUCTION(Dmul);
459  DEFINE_INSTRUCTION(Dmulh);
460  DEFINE_INSTRUCTION2(Mult);
461  DEFINE_INSTRUCTION2(Dmult);
462  DEFINE_INSTRUCTION2(Multu);
463  DEFINE_INSTRUCTION2(Dmultu);
464  DEFINE_INSTRUCTION2(Div);
465  DEFINE_INSTRUCTION2(Ddiv);
466  DEFINE_INSTRUCTION2(Divu);
467  DEFINE_INSTRUCTION2(Ddivu);
468 
469  DEFINE_INSTRUCTION(And);
470  DEFINE_INSTRUCTION(Or);
471  DEFINE_INSTRUCTION(Xor);
472  DEFINE_INSTRUCTION(Nor);
473  DEFINE_INSTRUCTION2(Neg);
474 
475  DEFINE_INSTRUCTION(Slt);
476  DEFINE_INSTRUCTION(Sltu);
477  DEFINE_INSTRUCTION(Sle);
478  DEFINE_INSTRUCTION(Sleu);
479  DEFINE_INSTRUCTION(Sgt);
480  DEFINE_INSTRUCTION(Sgtu);
481  DEFINE_INSTRUCTION(Sge);
482  DEFINE_INSTRUCTION(Sgeu);
483 
484  // MIPS32 R2 instruction macro.
485  DEFINE_INSTRUCTION(Ror);
486  DEFINE_INSTRUCTION(Dror);
487 
488 #undef DEFINE_INSTRUCTION
489 #undef DEFINE_INSTRUCTION2
490 #undef DEFINE_INSTRUCTION3
491 
492  void SmiUntag(Register dst, const MemOperand& src);
493  void SmiUntag(Register dst, Register src) {
494  if (SmiValuesAre32Bits()) {
495  dsra32(dst, src, kSmiShift - 32);
496  } else {
497  DCHECK(SmiValuesAre31Bits());
498  sra(dst, src, kSmiShift);
499  }
500  }
501 
502  void SmiUntag(Register reg) { SmiUntag(reg, reg); }
503 
504  // Removes current frame and its arguments from the stack preserving
505  // the arguments and a return address pushed to the stack for the next call.
506  // Both |callee_args_count| and |caller_args_count_reg| do not include
507  // receiver. |callee_args_count| is not modified, |caller_args_count_reg|
508  // is trashed.
509  void PrepareForTailCall(const ParameterCount& callee_args_count,
510  Register caller_args_count_reg, Register scratch0,
511  Register scratch1);
512 
513  int CalculateStackPassedWords(int num_reg_arguments,
514  int num_double_arguments);
515 
516  // Before calling a C-function from generated code, align arguments on stack
517  // and add space for the four mips argument slots.
518  // After aligning the frame, non-register arguments must be stored on the
519  // stack, after the argument-slots using helper: CFunctionArgumentOperand().
520  // The argument count assumes all arguments are word sized.
521  // Some compilers/platforms require the stack to be aligned when calling
522  // C++ code.
523  // Needs a scratch register to do some arithmetic. This register will be
524  // trashed.
525  void PrepareCallCFunction(int num_reg_arguments, int num_double_registers,
526  Register scratch);
527  void PrepareCallCFunction(int num_reg_arguments, Register scratch);
528 
529  // Arguments 1-4 are placed in registers a0 through a3 respectively.
530  // Arguments 5..n are stored to stack using following:
531  // Sw(a4, CFunctionArgumentOperand(5));
532 
533  // Calls a C function and cleans up the space for arguments allocated
534  // by PrepareCallCFunction. The called function is not allowed to trigger a
535  // garbage collection, since that might move the code and invalidate the
536  // return address (unless this is somehow accounted for by the called
537  // function).
538  void CallCFunction(ExternalReference function, int num_arguments);
539  void CallCFunction(Register function, int num_arguments);
540  void CallCFunction(ExternalReference function, int num_reg_arguments,
541  int num_double_arguments);
542  void CallCFunction(Register function, int num_reg_arguments,
543  int num_double_arguments);
544  void MovFromFloatResult(DoubleRegister dst);
545  void MovFromFloatParameter(DoubleRegister dst);
546 
547  // There are two ways of passing double arguments on MIPS, depending on
548  // whether soft or hard floating point ABI is used. These functions
549  // abstract parameter passing for the three different ways we call
550  // C functions from generated code.
551  void MovToFloatParameter(DoubleRegister src);
552  void MovToFloatParameters(DoubleRegister src1, DoubleRegister src2);
553  void MovToFloatResult(DoubleRegister src);
554 
555  // See comments at the beginning of Builtins::Generate_CEntry.
556  inline void PrepareCEntryArgs(int num_args) { li(a0, num_args); }
557  inline void PrepareCEntryFunction(const ExternalReference& ref) {
558  li(a1, ref);
559  }
560 
561  void CheckPageFlag(Register object, Register scratch, int mask, Condition cc,
562  Label* condition_met);
563 #undef COND_ARGS
564 
565  // Call a runtime routine. This expects {centry} to contain a fitting CEntry
566  // builtin for the target runtime function and uses an indirect call.
567  void CallRuntimeWithCEntry(Runtime::FunctionId fid, Register centry);
568 
569  // Performs a truncating conversion of a floating point number as used by
570  // the JS bitwise operations. See ECMA-262 9.5: ToInt32. Goes to 'done' if it
571  // succeeds, otherwise falls through if result is saturated. On return
572  // 'result' either holds answer, or is clobbered on fall through.
573  //
574  // Only public for the test code in test-code-stubs-arm.cc.
575  void TryInlineTruncateDoubleToI(Register result, DoubleRegister input,
576  Label* done);
577 
578  // Performs a truncating conversion of a floating point number as used by
579  // the JS bitwise operations. See ECMA-262 9.5: ToInt32.
580  // Exits with 'result' holding the answer.
581  void TruncateDoubleToI(Isolate* isolate, Zone* zone, Register result,
582  DoubleRegister double_input, StubCallMode stub_mode);
583 
584  // Conditional move.
585  void Movz(Register rd, Register rs, Register rt);
586  void Movn(Register rd, Register rs, Register rt);
587  void Movt(Register rd, Register rs, uint16_t cc = 0);
588  void Movf(Register rd, Register rs, uint16_t cc = 0);
589 
590  void LoadZeroIfFPUCondition(Register dest);
591  void LoadZeroIfNotFPUCondition(Register dest);
592 
593  void LoadZeroIfConditionNotZero(Register dest, Register condition);
594  void LoadZeroIfConditionZero(Register dest, Register condition);
595  void LoadZeroOnCondition(Register rd, Register rs, const Operand& rt,
596  Condition cond);
597 
598  void Clz(Register rd, Register rs);
599  void Ctz(Register rd, Register rs);
600  void Dctz(Register rd, Register rs);
601  void Popcnt(Register rd, Register rs);
602  void Dpopcnt(Register rd, Register rs);
603 
604  // MIPS64 R2 instruction macro.
605  void Ext(Register rt, Register rs, uint16_t pos, uint16_t size);
606  void Dext(Register rt, Register rs, uint16_t pos, uint16_t size);
607  void Ins(Register rt, Register rs, uint16_t pos, uint16_t size);
608  void Dins(Register rt, Register rs, uint16_t pos, uint16_t size);
609  void ExtractBits(Register dest, Register source, Register pos, int size,
610  bool sign_extend = false);
611  void InsertBits(Register dest, Register source, Register pos, int size);
612  void Neg_s(FPURegister fd, FPURegister fs);
613  void Neg_d(FPURegister fd, FPURegister fs);
614 
615  // MIPS64 R6 instruction macros.
616  void Bovc(Register rt, Register rs, Label* L);
617  void Bnvc(Register rt, Register rs, Label* L);
618 
619  // Convert single to unsigned word.
620  void Trunc_uw_s(FPURegister fd, FPURegister fs, FPURegister scratch);
621  void Trunc_uw_s(Register rd, FPURegister fs, FPURegister scratch);
622 
623  // Change endianness
624  void ByteSwapSigned(Register dest, Register src, int operand_size);
625  void ByteSwapUnsigned(Register dest, Register src, int operand_size);
626 
627  void Ulh(Register rd, const MemOperand& rs);
628  void Ulhu(Register rd, const MemOperand& rs);
629  void Ush(Register rd, const MemOperand& rs, Register scratch);
630 
631  void Ulw(Register rd, const MemOperand& rs);
632  void Ulwu(Register rd, const MemOperand& rs);
633  void Usw(Register rd, const MemOperand& rs);
634 
635  void Uld(Register rd, const MemOperand& rs);
636  void Usd(Register rd, const MemOperand& rs);
637 
638  void Ulwc1(FPURegister fd, const MemOperand& rs, Register scratch);
639  void Uswc1(FPURegister fd, const MemOperand& rs, Register scratch);
640 
641  void Uldc1(FPURegister fd, const MemOperand& rs, Register scratch);
642  void Usdc1(FPURegister fd, const MemOperand& rs, Register scratch);
643 
644  void Lb(Register rd, const MemOperand& rs);
645  void Lbu(Register rd, const MemOperand& rs);
646  void Sb(Register rd, const MemOperand& rs);
647 
648  void Lh(Register rd, const MemOperand& rs);
649  void Lhu(Register rd, const MemOperand& rs);
650  void Sh(Register rd, const MemOperand& rs);
651 
652  void Lw(Register rd, const MemOperand& rs);
653  void Lwu(Register rd, const MemOperand& rs);
654  void Sw(Register rd, const MemOperand& rs);
655 
656  void Lwc1(FPURegister fd, const MemOperand& src);
657  void Swc1(FPURegister fs, const MemOperand& dst);
658 
659  void Ldc1(FPURegister fd, const MemOperand& src);
660  void Sdc1(FPURegister fs, const MemOperand& dst);
661 
662  void Ll(Register rd, const MemOperand& rs);
663  void Sc(Register rd, const MemOperand& rs);
664 
665  void Lld(Register rd, const MemOperand& rs);
666  void Scd(Register rd, const MemOperand& rs);
667 
668  // Perform a floating-point min or max operation with the
669  // (IEEE-754-compatible) semantics of MIPS32's Release 6 MIN.fmt/MAX.fmt.
670  // Some cases, typically NaNs or +/-0.0, are expected to be rare and are
671  // handled in out-of-line code. The specific behaviour depends on supported
672  // instructions.
673  //
674  // These functions assume (and assert) that src1!=src2. It is permitted
675  // for the result to alias either input register.
676  void Float32Max(FPURegister dst, FPURegister src1, FPURegister src2,
677  Label* out_of_line);
678  void Float32Min(FPURegister dst, FPURegister src1, FPURegister src2,
679  Label* out_of_line);
680  void Float64Max(FPURegister dst, FPURegister src1, FPURegister src2,
681  Label* out_of_line);
682  void Float64Min(FPURegister dst, FPURegister src1, FPURegister src2,
683  Label* out_of_line);
684 
685  // Generate out-of-line cases for the macros above.
686  void Float32MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2);
687  void Float32MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2);
688  void Float64MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2);
689  void Float64MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2);
690 
691  bool IsDoubleZeroRegSet() { return has_double_zero_reg_set_; }
692 
693  void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); }
694 
695  inline void Move(Register dst, Handle<HeapObject> handle) { li(dst, handle); }
696  inline void Move(Register dst, Smi smi) { li(dst, Operand(smi)); }
697 
698  inline void Move(Register dst, Register src) {
699  if (dst != src) {
700  mov(dst, src);
701  }
702  }
703 
704  inline void Move(FPURegister dst, FPURegister src) { Move_d(dst, src); }
705 
706  inline void Move(Register dst_low, Register dst_high, FPURegister src) {
707  mfc1(dst_low, src);
708  mfhc1(dst_high, src);
709  }
710 
711  inline void Move(Register dst, FPURegister src) { dmfc1(dst, src); }
712 
713  inline void Move(FPURegister dst, Register src) { dmtc1(src, dst); }
714 
715  inline void FmoveHigh(Register dst_high, FPURegister src) {
716  mfhc1(dst_high, src);
717  }
718 
719  inline void FmoveHigh(FPURegister dst, Register src_high) {
720  mthc1(src_high, dst);
721  }
722 
723  inline void FmoveLow(Register dst_low, FPURegister src) {
724  mfc1(dst_low, src);
725  }
726 
727  void FmoveLow(FPURegister dst, Register src_low);
728 
729  inline void Move(FPURegister dst, Register src_low, Register src_high) {
730  mtc1(src_low, dst);
731  mthc1(src_high, dst);
732  }
733 
734  inline void Move_d(FPURegister dst, FPURegister src) {
735  if (dst != src) {
736  mov_d(dst, src);
737  }
738  }
739 
740  inline void Move_s(FPURegister dst, FPURegister src) {
741  if (dst != src) {
742  mov_s(dst, src);
743  }
744  }
745 
746  void Move(FPURegister dst, float imm) { Move(dst, bit_cast<uint32_t>(imm)); }
747  void Move(FPURegister dst, double imm) { Move(dst, bit_cast<uint64_t>(imm)); }
748  void Move(FPURegister dst, uint32_t src);
749  void Move(FPURegister dst, uint64_t src);
750 
751  // DaddOverflow sets overflow register to a negative value if
752  // overflow occured, otherwise it is zero or positive
753  void DaddOverflow(Register dst, Register left, const Operand& right,
754  Register overflow);
755  // DsubOverflow sets overflow register to a negative value if
756  // overflow occured, otherwise it is zero or positive
757  void DsubOverflow(Register dst, Register left, const Operand& right,
758  Register overflow);
759  // MulOverflow sets overflow register to zero if no overflow occured
760  void MulOverflow(Register dst, Register left, const Operand& right,
761  Register overflow);
762 
763 // Number of instructions needed for calculation of switch table entry address
764 #ifdef _MIPS_ARCH_MIPS64R6
765  static const int kSwitchTablePrologueSize = 6;
766 #else
767  static const int kSwitchTablePrologueSize = 11;
768 #endif
769 
770  // GetLabelFunction must be lambda '[](size_t index) -> Label*' or a
771  // functor/function with 'Label *func(size_t index)' declaration.
772  template <typename Func>
773  void GenerateSwitchTable(Register index, size_t case_count,
774  Func GetLabelFunction);
775 
776  // Load an object from the root table.
777  void LoadRoot(Register destination, RootIndex index) override;
778  void LoadRoot(Register destination, RootIndex index, Condition cond,
779  Register src1, const Operand& src2);
780 
781  // If the value is a NaN, canonicalize the value else, do nothing.
782  void FPUCanonicalizeNaN(const DoubleRegister dst, const DoubleRegister src);
783 
784  // ---------------------------------------------------------------------------
785  // FPU macros. These do not handle special cases like NaN or +- inf.
786 
787  // Convert unsigned word to double.
788  void Cvt_d_uw(FPURegister fd, FPURegister fs);
789  void Cvt_d_uw(FPURegister fd, Register rs);
790 
791  // Convert unsigned long to double.
792  void Cvt_d_ul(FPURegister fd, FPURegister fs);
793  void Cvt_d_ul(FPURegister fd, Register rs);
794 
795  // Convert unsigned word to float.
796  void Cvt_s_uw(FPURegister fd, FPURegister fs);
797  void Cvt_s_uw(FPURegister fd, Register rs);
798 
799  // Convert unsigned long to float.
800  void Cvt_s_ul(FPURegister fd, FPURegister fs);
801  void Cvt_s_ul(FPURegister fd, Register rs);
802 
803  // Convert double to unsigned word.
804  void Trunc_uw_d(FPURegister fd, FPURegister fs, FPURegister scratch);
805  void Trunc_uw_d(Register rd, FPURegister fs, FPURegister scratch);
806 
807  // Convert double to unsigned long.
808  void Trunc_ul_d(FPURegister fd, FPURegister fs, FPURegister scratch,
809  Register result = no_reg);
810  void Trunc_ul_d(Register rd, FPURegister fs, FPURegister scratch,
811  Register result = no_reg);
812 
813  // Convert single to unsigned long.
814  void Trunc_ul_s(FPURegister fd, FPURegister fs, FPURegister scratch,
815  Register result = no_reg);
816  void Trunc_ul_s(Register rd, FPURegister fs, FPURegister scratch,
817  Register result = no_reg);
818 
819  // Round double functions
820  void Trunc_d_d(FPURegister fd, FPURegister fs);
821  void Round_d_d(FPURegister fd, FPURegister fs);
822  void Floor_d_d(FPURegister fd, FPURegister fs);
823  void Ceil_d_d(FPURegister fd, FPURegister fs);
824 
825  // Round float functions
826  void Trunc_s_s(FPURegister fd, FPURegister fs);
827  void Round_s_s(FPURegister fd, FPURegister fs);
828  void Floor_s_s(FPURegister fd, FPURegister fs);
829  void Ceil_s_s(FPURegister fd, FPURegister fs);
830 
831  // Jump the register contains a smi.
832  void JumpIfSmi(Register value, Label* smi_label, Register scratch = at,
833  BranchDelaySlot bd = PROTECT);
834 
835  void JumpIfEqual(Register a, int32_t b, Label* dest) {
836  li(kScratchReg, Operand(b));
837  Branch(dest, eq, a, Operand(kScratchReg));
838  }
839 
840  void JumpIfLessThan(Register a, int32_t b, Label* dest) {
841  li(kScratchReg, Operand(b));
842  Branch(dest, lt, a, Operand(kScratchReg));
843  }
844 
845  // Push a standard frame, consisting of ra, fp, context and JS function.
846  void PushStandardFrame(Register function_reg);
847 
848  // Get the actual activation frame alignment for target environment.
849  static int ActivationFrameAlignment();
850 
851  // Load Scaled Address instructions. Parameter sa (shift argument) must be
852  // between [1, 31] (inclusive). On pre-r6 architectures the scratch register
853  // may be clobbered.
854  void Lsa(Register rd, Register rs, Register rt, uint8_t sa,
855  Register scratch = at);
856  void Dlsa(Register rd, Register rs, Register rt, uint8_t sa,
857  Register scratch = at);
858 
859  // Compute the start of the generated instruction stream from the current PC.
860  // This is an alternative to embedding the {CodeObject} handle as a reference.
861  void ComputeCodeStartAddress(Register dst);
862 
863  void ResetSpeculationPoisonRegister();
864 
865  protected:
866  inline Register GetRtAsRegisterHelper(const Operand& rt, Register scratch);
867  inline int32_t GetOffset(int32_t offset, Label* L, OffsetSize bits);
868 
869  private:
870  bool has_double_zero_reg_set_ = false;
871 
872  void CompareF(SecondaryField sizeField, FPUCondition cc, FPURegister cmp1,
873  FPURegister cmp2);
874 
875  void CompareIsNanF(SecondaryField sizeField, FPURegister cmp1,
876  FPURegister cmp2);
877 
878  void BranchShortMSA(MSABranchDF df, Label* target, MSABranchCondition cond,
879  MSARegister wt, BranchDelaySlot bd = PROTECT);
880 
881  void CallCFunctionHelper(Register function, int num_reg_arguments,
882  int num_double_arguments);
883 
884  bool CalculateOffset(Label* L, int32_t& offset, OffsetSize bits);
885  bool CalculateOffset(Label* L, int32_t& offset, OffsetSize bits,
886  Register& scratch, const Operand& rt);
887 
888  void BranchShortHelperR6(int32_t offset, Label* L);
889  void BranchShortHelper(int16_t offset, Label* L, BranchDelaySlot bdslot);
890  bool BranchShortHelperR6(int32_t offset, Label* L, Condition cond,
891  Register rs, const Operand& rt);
892  bool BranchShortHelper(int16_t offset, Label* L, Condition cond, Register rs,
893  const Operand& rt, BranchDelaySlot bdslot);
894  bool BranchShortCheck(int32_t offset, Label* L, Condition cond, Register rs,
895  const Operand& rt, BranchDelaySlot bdslot);
896 
897  void BranchAndLinkShortHelperR6(int32_t offset, Label* L);
898  void BranchAndLinkShortHelper(int16_t offset, Label* L,
899  BranchDelaySlot bdslot);
900  void BranchAndLinkShort(int32_t offset, BranchDelaySlot bdslot = PROTECT);
901  void BranchAndLinkShort(Label* L, BranchDelaySlot bdslot = PROTECT);
902  bool BranchAndLinkShortHelperR6(int32_t offset, Label* L, Condition cond,
903  Register rs, const Operand& rt);
904  bool BranchAndLinkShortHelper(int16_t offset, Label* L, Condition cond,
905  Register rs, const Operand& rt,
906  BranchDelaySlot bdslot);
907  bool BranchAndLinkShortCheck(int32_t offset, Label* L, Condition cond,
908  Register rs, const Operand& rt,
909  BranchDelaySlot bdslot);
910  void BranchLong(Label* L, BranchDelaySlot bdslot);
911  void BranchAndLinkLong(Label* L, BranchDelaySlot bdslot);
912 
913  template <typename RoundFunc>
914  void RoundDouble(FPURegister dst, FPURegister src, FPURoundingMode mode,
915  RoundFunc round);
916 
917  template <typename RoundFunc>
918  void RoundFloat(FPURegister dst, FPURegister src, FPURoundingMode mode,
919  RoundFunc round);
920 
921  // Push a fixed frame, consisting of ra, fp.
922  void PushCommonFrame(Register marker_reg = no_reg);
923 
924  void CallRecordWriteStub(Register object, Register address,
925  RememberedSetAction remembered_set_action,
926  SaveFPRegsMode fp_mode, Handle<Code> code_target,
927  Address wasm_target);
928 };
929 
930 // MacroAssembler implements a collection of frequently used macros.
931 class MacroAssembler : public TurboAssembler {
932  public:
933  MacroAssembler(const AssemblerOptions& options, void* buffer, int size)
934  : TurboAssembler(options, buffer, size) {}
935 
936  MacroAssembler(Isolate* isolate, void* buffer, int size,
937  CodeObjectRequired create_code_object)
938  : MacroAssembler(isolate, AssemblerOptions::Default(isolate), buffer,
939  size, create_code_object) {}
940 
941  MacroAssembler(Isolate* isolate, const AssemblerOptions& options,
942  void* buffer, int size, CodeObjectRequired create_code_object);
943 
944  bool IsNear(Label* L, Condition cond, int rs_reg);
945 
946  // Swap two registers. If the scratch register is omitted then a slightly
947  // less efficient form using xor instead of mov is emitted.
948  void Swap(Register reg1, Register reg2, Register scratch = no_reg);
949 
950  void PushRoot(RootIndex index) {
951  UseScratchRegisterScope temps(this);
952  Register scratch = temps.Acquire();
953  LoadRoot(scratch, index);
954  Push(scratch);
955  }
956 
957  // Compare the object in a register to a value and jump if they are equal.
958  void JumpIfRoot(Register with, RootIndex index, Label* if_equal) {
959  UseScratchRegisterScope temps(this);
960  Register scratch = temps.Acquire();
961  LoadRoot(scratch, index);
962  Branch(if_equal, eq, with, Operand(scratch));
963  }
964 
965  // Compare the object in a register to a value and jump if they are not equal.
966  void JumpIfNotRoot(Register with, RootIndex index, Label* if_not_equal) {
967  UseScratchRegisterScope temps(this);
968  Register scratch = temps.Acquire();
969  LoadRoot(scratch, index);
970  Branch(if_not_equal, ne, with, Operand(scratch));
971  }
972 
973  // ---------------------------------------------------------------------------
974  // GC Support
975 
976  // Notify the garbage collector that we wrote a pointer into an object.
977  // |object| is the object being stored into, |value| is the object being
978  // stored. value and scratch registers are clobbered by the operation.
979  // The offset is the offset from the start of the object, not the offset from
980  // the tagged HeapObject pointer. For use with FieldOperand(reg, off).
981  void RecordWriteField(
982  Register object, int offset, Register value, Register scratch,
983  RAStatus ra_status, SaveFPRegsMode save_fp,
984  RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET,
985  SmiCheck smi_check = INLINE_SMI_CHECK);
986 
987  // For a given |object| notify the garbage collector that the slot |address|
988  // has been written. |value| is the object being stored. The value and
989  // address registers are clobbered by the operation.
990  void RecordWrite(
991  Register object, Register address, Register value, RAStatus ra_status,
992  SaveFPRegsMode save_fp,
993  RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET,
994  SmiCheck smi_check = INLINE_SMI_CHECK);
995 
996  void Pref(int32_t hint, const MemOperand& rs);
997 
998  // ---------------------------------------------------------------------------
999  // Pseudo-instructions.
1000 
1001  void LoadWordPair(Register rd, const MemOperand& rs, Register scratch = at);
1002  void StoreWordPair(Register rd, const MemOperand& rs, Register scratch = at);
1003 
1004  // Push and pop the registers that can hold pointers, as defined by the
1005  // RegList constant kSafepointSavedRegisters.
1006  void PushSafepointRegisters();
1007  void PopSafepointRegisters();
1008 
1009  // Convert double to unsigned long.
1010  void Trunc_l_ud(FPURegister fd, FPURegister fs, FPURegister scratch);
1011 
1012  void Trunc_l_d(FPURegister fd, FPURegister fs);
1013  void Round_l_d(FPURegister fd, FPURegister fs);
1014  void Floor_l_d(FPURegister fd, FPURegister fs);
1015  void Ceil_l_d(FPURegister fd, FPURegister fs);
1016 
1017  void Trunc_w_d(FPURegister fd, FPURegister fs);
1018  void Round_w_d(FPURegister fd, FPURegister fs);
1019  void Floor_w_d(FPURegister fd, FPURegister fs);
1020  void Ceil_w_d(FPURegister fd, FPURegister fs);
1021 
1022  void Madd_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft,
1023  FPURegister scratch);
1024  void Madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft,
1025  FPURegister scratch);
1026  void Msub_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft,
1027  FPURegister scratch);
1028  void Msub_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft,
1029  FPURegister scratch);
1030 
1031  void BranchShortMSA(MSABranchDF df, Label* target, MSABranchCondition cond,
1032  MSARegister wt, BranchDelaySlot bd = PROTECT);
1033 
1034  // Truncates a double using a specific rounding mode, and writes the value
1035  // to the result register.
1036  // The except_flag will contain any exceptions caused by the instruction.
1037  // If check_inexact is kDontCheckForInexactConversion, then the inexact
1038  // exception is masked.
1039  void EmitFPUTruncate(
1040  FPURoundingMode rounding_mode, Register result,
1041  DoubleRegister double_input, Register scratch,
1042  DoubleRegister double_scratch, Register except_flag,
1043  CheckForInexactConversion check_inexact = kDontCheckForInexactConversion);
1044 
1045  // Enter exit frame.
1046  // argc - argument count to be dropped by LeaveExitFrame.
1047  // save_doubles - saves FPU registers on stack, currently disabled.
1048  // stack_space - extra stack space.
1049  void EnterExitFrame(bool save_doubles, int stack_space = 0,
1050  StackFrame::Type frame_type = StackFrame::EXIT);
1051 
1052  // Leave the current exit frame.
1053  void LeaveExitFrame(bool save_doubles, Register arg_count,
1054  bool do_return = NO_EMIT_RETURN,
1055  bool argument_count_is_length = false);
1056 
1057  // Make sure the stack is aligned. Only emits code in debug mode.
1058  void AssertStackIsAligned();
1059 
1060  // Load the global proxy from the current context.
1061  void LoadGlobalProxy(Register dst) {
1062  LoadNativeContextSlot(Context::GLOBAL_PROXY_INDEX, dst);
1063  }
1064 
1065  void LoadNativeContextSlot(int index, Register dst);
1066 
1067  // Load the initial map from the global function. The registers
1068  // function and map can be the same, function is then overwritten.
1069  void LoadGlobalFunctionInitialMap(Register function,
1070  Register map,
1071  Register scratch);
1072 
1073  // -------------------------------------------------------------------------
1074  // JavaScript invokes.
1075 
1076  // Invoke the JavaScript function code by either calling or jumping.
1077  void InvokeFunctionCode(Register function, Register new_target,
1078  const ParameterCount& expected,
1079  const ParameterCount& actual, InvokeFlag flag);
1080 
1081  // On function call, call into the debugger if necessary.
1082  void CheckDebugHook(Register fun, Register new_target,
1083  const ParameterCount& expected,
1084  const ParameterCount& actual);
1085 
1086  // Invoke the JavaScript function in the given register. Changes the
1087  // current context to the context in the function before invoking.
1088  void InvokeFunction(Register function, Register new_target,
1089  const ParameterCount& actual, InvokeFlag flag);
1090 
1091  void InvokeFunction(Register function, const ParameterCount& expected,
1092  const ParameterCount& actual, InvokeFlag flag);
1093 
1094  // Frame restart support.
1095  void MaybeDropFrames();
1096 
1097  // Exception handling.
1098 
1099  // Push a new stack handler and link into stack handler chain.
1100  void PushStackHandler();
1101 
1102  // Unlink the stack handler on top of the stack from the stack handler chain.
1103  // Must preserve the result register.
1104  void PopStackHandler();
1105 
1106  // -------------------------------------------------------------------------
1107  // Support functions.
1108 
1109  void GetObjectType(Register function,
1110  Register map,
1111  Register type_reg);
1112 
1113  // -------------------------------------------------------------------------
1114  // Runtime calls.
1115 
1116 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \
1117 const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
1118 
1119  // Call a code stub.
1120  void CallStub(CodeStub* stub, COND_ARGS);
1121 
1122  // Tail call a code stub (jump).
1123  void TailCallStub(CodeStub* stub, COND_ARGS);
1124 
1125 #undef COND_ARGS
1126 
1127  // Call a runtime routine.
1128  void CallRuntime(const Runtime::Function* f, int num_arguments,
1129  SaveFPRegsMode save_doubles = kDontSaveFPRegs);
1130 
1131  // Convenience function: Same as above, but takes the fid instead.
1132  void CallRuntime(Runtime::FunctionId fid,
1133  SaveFPRegsMode save_doubles = kDontSaveFPRegs) {
1134  const Runtime::Function* function = Runtime::FunctionForId(fid);
1135  CallRuntime(function, function->nargs, save_doubles);
1136  }
1137 
1138  // Convenience function: Same as above, but takes the fid instead.
1139  void CallRuntime(Runtime::FunctionId fid, int num_arguments,
1140  SaveFPRegsMode save_doubles = kDontSaveFPRegs) {
1141  CallRuntime(Runtime::FunctionForId(fid), num_arguments, save_doubles);
1142  }
1143 
1144  // Convenience function: tail call a runtime routine (jump).
1145  void TailCallRuntime(Runtime::FunctionId fid);
1146 
1147  // Jump to the builtin routine.
1148  void JumpToExternalReference(const ExternalReference& builtin,
1149  BranchDelaySlot bd = PROTECT,
1150  bool builtin_exit_frame = false);
1151 
1152  // Generates a trampoline to jump to the off-heap instruction stream.
1153  void JumpToInstructionStream(Address entry);
1154 
1155  // ---------------------------------------------------------------------------
1156  // In-place weak references.
1157  void LoadWeakValue(Register out, Register in, Label* target_if_cleared);
1158 
1159  // -------------------------------------------------------------------------
1160  // StatsCounter support.
1161 
1162  void IncrementCounter(StatsCounter* counter, int value,
1163  Register scratch1, Register scratch2);
1164  void DecrementCounter(StatsCounter* counter, int value,
1165  Register scratch1, Register scratch2);
1166 
1167  // -------------------------------------------------------------------------
1168  // Smi utilities.
1169 
1170  void SmiTag(Register dst, Register src) {
1171  STATIC_ASSERT(kSmiTag == 0);
1172  if (SmiValuesAre32Bits()) {
1173  dsll32(dst, src, 0);
1174  } else {
1175  DCHECK(SmiValuesAre31Bits());
1176  Addu(dst, src, src);
1177  }
1178  }
1179 
1180  void SmiTag(Register reg) {
1181  SmiTag(reg, reg);
1182  }
1183 
1184  // Left-shifted from int32 equivalent of Smi.
1185  void SmiScale(Register dst, Register src, int scale) {
1186  if (SmiValuesAre32Bits()) {
1187  // The int portion is upper 32-bits of 64-bit word.
1188  dsra(dst, src, kSmiShift - scale);
1189  } else {
1190  DCHECK(SmiValuesAre31Bits());
1191  DCHECK_GE(scale, kSmiTagSize);
1192  sll(dst, src, scale - kSmiTagSize);
1193  }
1194  }
1195 
1196  // Test if the register contains a smi.
1197  inline void SmiTst(Register value, Register scratch) {
1198  And(scratch, value, Operand(kSmiTagMask));
1199  }
1200  // Untag the source value into destination and jump if source is a smi.
1201  // Source and destination can be the same register.
1202  void UntagAndJumpIfSmi(Register dst, Register src, Label* smi_case);
1203 
1204  // Jump if the register contains a non-smi.
1205  void JumpIfNotSmi(Register value,
1206  Label* not_smi_label,
1207  Register scratch = at,
1208  BranchDelaySlot bd = PROTECT);
1209 
1210  // Jump if either of the registers contain a smi.
1211  void JumpIfEitherSmi(Register reg1, Register reg2, Label* on_either_smi);
1212 
1213  // Abort execution if argument is a smi, enabled via --debug-code.
1214  void AssertNotSmi(Register object);
1215  void AssertSmi(Register object);
1216 
1217  // Abort execution if argument is not a Constructor, enabled via --debug-code.
1218  void AssertConstructor(Register object);
1219 
1220  // Abort execution if argument is not a JSFunction, enabled via --debug-code.
1221  void AssertFunction(Register object);
1222 
1223  // Abort execution if argument is not a JSBoundFunction,
1224  // enabled via --debug-code.
1225  void AssertBoundFunction(Register object);
1226 
1227  // Abort execution if argument is not a JSGeneratorObject (or subclass),
1228  // enabled via --debug-code.
1229  void AssertGeneratorObject(Register object);
1230 
1231  // Abort execution if argument is not undefined or an AllocationSite, enabled
1232  // via --debug-code.
1233  void AssertUndefinedOrAllocationSite(Register object, Register scratch);
1234 
1235  template<typename Field>
1236  void DecodeField(Register dst, Register src) {
1237  Ext(dst, src, Field::kShift, Field::kSize);
1238  }
1239 
1240  template<typename Field>
1241  void DecodeField(Register reg) {
1242  DecodeField<Field>(reg, reg);
1243  }
1244 
1245  private:
1246  // Helper functions for generating invokes.
1247  void InvokePrologue(const ParameterCount& expected,
1248  const ParameterCount& actual, Label* done,
1249  bool* definitely_mismatches, InvokeFlag flag);
1250 
1251  // Compute memory operands for safepoint stack slots.
1252  static int SafepointRegisterStackIndex(int reg_code);
1253 
1254  // Needs access to SafepointRegisterStackIndex for compiled frame
1255  // traversal.
1256  friend class StandardFrame;
1257 };
1258 
1259 template <typename Func>
1260 void TurboAssembler::GenerateSwitchTable(Register index, size_t case_count,
1261  Func GetLabelFunction) {
1262  // Ensure that dd-ed labels following this instruction use 8 bytes aligned
1263  // addresses.
1264  BlockTrampolinePoolFor(static_cast<int>(case_count) * 2 +
1265  kSwitchTablePrologueSize);
1266  UseScratchRegisterScope temps(this);
1267  Register scratch = temps.Acquire();
1268  if (kArchVariant >= kMips64r6) {
1269  // Opposite of Align(8) as we have odd number of instructions in this case.
1270  if ((pc_offset() & 7) == 0) {
1271  nop();
1272  }
1273  addiupc(scratch, 5);
1274  Dlsa(scratch, scratch, index, kPointerSizeLog2);
1275  Ld(scratch, MemOperand(scratch));
1276  } else {
1277  Label here;
1278  Align(8);
1279  push(ra);
1280  bal(&here);
1281  dsll(scratch, index, kPointerSizeLog2); // Branch delay slot.
1282  bind(&here);
1283  daddu(scratch, scratch, ra);
1284  pop(ra);
1285  Ld(scratch, MemOperand(scratch, 6 * v8::internal::kInstrSize));
1286  }
1287  jr(scratch);
1288  nop(); // Branch delay slot nop.
1289  for (size_t index = 0; index < case_count; ++index) {
1290  dd(GetLabelFunction(index));
1291  }
1292 }
1293 
1294 #define ACCESS_MASM(masm) masm->
1295 
1296 } // namespace internal
1297 } // namespace v8
1298 
1299 #endif // V8_MIPS64_MACRO_ASSEMBLER_MIPS64_H_
Definition: libplatform.h:13