V8 API Reference, 7.2.502.16 (for Deno 0.2.4)
instruction-codes-mips.h
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// Copyright 2014 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#ifndef V8_COMPILER_BACKEND_MIPS_INSTRUCTION_CODES_MIPS_H_
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#define V8_COMPILER_BACKEND_MIPS_INSTRUCTION_CODES_MIPS_H_
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namespace
v8
{
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namespace
internal {
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namespace
compiler {
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// MIPS-specific opcodes that specify which assembly sequence to emit.
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// Most opcodes specify a single instruction.
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#define TARGET_ARCH_OPCODE_LIST(V) \
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V(MipsAdd) \
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V(MipsAddOvf) \
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V(MipsSub) \
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V(MipsSubOvf) \
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V(MipsMul) \
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V(MipsMulOvf) \
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V(MipsMulHigh) \
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V(MipsMulHighU) \
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V(MipsDiv) \
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V(MipsDivU) \
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V(MipsMod) \
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V(MipsModU) \
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V(MipsAnd) \
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V(MipsOr) \
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V(MipsNor) \
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V(MipsXor) \
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V(MipsClz) \
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V(MipsCtz) \
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V(MipsPopcnt) \
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V(MipsLsa) \
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V(MipsShl) \
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V(MipsShr) \
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V(MipsSar) \
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V(MipsShlPair) \
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V(MipsShrPair) \
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V(MipsSarPair) \
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V(MipsExt) \
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V(MipsIns) \
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V(MipsRor) \
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V(MipsMov) \
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V(MipsTst) \
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V(MipsCmp) \
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V(MipsCmpS) \
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V(MipsAddS) \
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V(MipsSubS) \
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V(MipsMulS) \
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V(MipsDivS) \
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V(MipsModS) \
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V(MipsAbsS) \
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V(MipsSqrtS) \
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V(MipsMaxS) \
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V(MipsMinS) \
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V(MipsCmpD) \
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V(MipsAddD) \
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V(MipsSubD) \
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V(MipsMulD) \
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V(MipsDivD) \
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V(MipsModD) \
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V(MipsAbsD) \
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V(MipsSqrtD) \
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V(MipsMaxD) \
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V(MipsMinD) \
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V(MipsNegS) \
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V(MipsNegD) \
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V(MipsAddPair) \
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V(MipsSubPair) \
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V(MipsMulPair) \
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V(MipsMaddS) \
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V(MipsMaddD) \
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V(MipsMsubS) \
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V(MipsMsubD) \
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V(MipsFloat32RoundDown) \
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V(MipsFloat32RoundTruncate) \
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V(MipsFloat32RoundUp) \
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V(MipsFloat32RoundTiesEven) \
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V(MipsFloat64RoundDown) \
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V(MipsFloat64RoundTruncate) \
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V(MipsFloat64RoundUp) \
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V(MipsFloat64RoundTiesEven) \
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V(MipsCvtSD) \
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V(MipsCvtDS) \
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V(MipsTruncWD) \
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V(MipsRoundWD) \
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V(MipsFloorWD) \
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V(MipsCeilWD) \
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V(MipsTruncWS) \
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V(MipsRoundWS) \
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V(MipsFloorWS) \
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V(MipsCeilWS) \
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V(MipsTruncUwD) \
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V(MipsTruncUwS) \
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V(MipsCvtDW) \
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V(MipsCvtDUw) \
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V(MipsCvtSW) \
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V(MipsCvtSUw) \
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V(MipsLb) \
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V(MipsLbu) \
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V(MipsSb) \
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V(MipsLh) \
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V(MipsUlh) \
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V(MipsLhu) \
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V(MipsUlhu) \
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V(MipsSh) \
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V(MipsUsh) \
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V(MipsLw) \
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V(MipsUlw) \
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V(MipsSw) \
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V(MipsUsw) \
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V(MipsLwc1) \
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V(MipsUlwc1) \
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V(MipsSwc1) \
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V(MipsUswc1) \
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V(MipsLdc1) \
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V(MipsUldc1) \
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V(MipsSdc1) \
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V(MipsUsdc1) \
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V(MipsFloat64ExtractLowWord32) \
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V(MipsFloat64ExtractHighWord32) \
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V(MipsFloat64InsertLowWord32) \
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V(MipsFloat64InsertHighWord32) \
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V(MipsFloat64SilenceNaN) \
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V(MipsFloat32Max) \
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V(MipsFloat64Max) \
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V(MipsFloat32Min) \
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V(MipsFloat64Min) \
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V(MipsPush) \
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V(MipsPeek) \
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V(MipsStoreToStackSlot) \
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V(MipsByteSwap32) \
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V(MipsStackClaim) \
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V(MipsSeb) \
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V(MipsSeh) \
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V(MipsS128Zero) \
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V(MipsI32x4Splat) \
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V(MipsI32x4ExtractLane) \
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V(MipsI32x4ReplaceLane) \
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V(MipsI32x4Add) \
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V(MipsI32x4AddHoriz) \
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V(MipsI32x4Sub) \
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V(MipsF32x4Splat) \
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V(MipsF32x4ExtractLane) \
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V(MipsF32x4ReplaceLane) \
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V(MipsF32x4SConvertI32x4) \
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V(MipsF32x4UConvertI32x4) \
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V(MipsI32x4Mul) \
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V(MipsI32x4MaxS) \
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V(MipsI32x4MinS) \
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V(MipsI32x4Eq) \
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V(MipsI32x4Ne) \
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V(MipsI32x4Shl) \
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V(MipsI32x4ShrS) \
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V(MipsI32x4ShrU) \
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V(MipsI32x4MaxU) \
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V(MipsI32x4MinU) \
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V(MipsF32x4Abs) \
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V(MipsF32x4Neg) \
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V(MipsF32x4RecipApprox) \
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V(MipsF32x4RecipSqrtApprox) \
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V(MipsF32x4Add) \
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V(MipsF32x4AddHoriz) \
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V(MipsF32x4Sub) \
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V(MipsF32x4Mul) \
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V(MipsF32x4Max) \
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V(MipsF32x4Min) \
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V(MipsF32x4Eq) \
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V(MipsF32x4Ne) \
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V(MipsF32x4Lt) \
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V(MipsF32x4Le) \
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V(MipsI32x4SConvertF32x4) \
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V(MipsI32x4UConvertF32x4) \
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V(MipsI32x4Neg) \
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V(MipsI32x4GtS) \
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V(MipsI32x4GeS) \
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V(MipsI32x4GtU) \
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V(MipsI32x4GeU) \
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V(MipsI16x8Splat) \
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V(MipsI16x8ExtractLane) \
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V(MipsI16x8ReplaceLane) \
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V(MipsI16x8Neg) \
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V(MipsI16x8Shl) \
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V(MipsI16x8ShrS) \
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V(MipsI16x8ShrU) \
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V(MipsI16x8Add) \
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V(MipsI16x8AddSaturateS) \
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V(MipsI16x8AddHoriz) \
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V(MipsI16x8Sub) \
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V(MipsI16x8SubSaturateS) \
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V(MipsI16x8Mul) \
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V(MipsI16x8MaxS) \
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V(MipsI16x8MinS) \
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V(MipsI16x8Eq) \
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V(MipsI16x8Ne) \
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V(MipsI16x8GtS) \
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V(MipsI16x8GeS) \
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V(MipsI16x8AddSaturateU) \
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V(MipsI16x8SubSaturateU) \
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V(MipsI16x8MaxU) \
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V(MipsI16x8MinU) \
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V(MipsI16x8GtU) \
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V(MipsI16x8GeU) \
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V(MipsI8x16Splat) \
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V(MipsI8x16ExtractLane) \
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V(MipsI8x16ReplaceLane) \
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V(MipsI8x16Neg) \
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V(MipsI8x16Shl) \
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V(MipsI8x16ShrS) \
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V(MipsI8x16Add) \
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V(MipsI8x16AddSaturateS) \
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V(MipsI8x16Sub) \
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V(MipsI8x16SubSaturateS) \
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V(MipsI8x16Mul) \
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V(MipsI8x16MaxS) \
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V(MipsI8x16MinS) \
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V(MipsI8x16Eq) \
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V(MipsI8x16Ne) \
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V(MipsI8x16GtS) \
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V(MipsI8x16GeS) \
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V(MipsI8x16ShrU) \
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V(MipsI8x16AddSaturateU) \
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V(MipsI8x16SubSaturateU) \
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V(MipsI8x16MaxU) \
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V(MipsI8x16MinU) \
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V(MipsI8x16GtU) \
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V(MipsI8x16GeU) \
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V(MipsS128And) \
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V(MipsS128Or) \
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V(MipsS128Xor) \
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V(MipsS128Not) \
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V(MipsS128Select) \
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V(MipsS1x4AnyTrue) \
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V(MipsS1x4AllTrue) \
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V(MipsS1x8AnyTrue) \
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V(MipsS1x8AllTrue) \
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V(MipsS1x16AnyTrue) \
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V(MipsS1x16AllTrue) \
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V(MipsS32x4InterleaveRight) \
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V(MipsS32x4InterleaveLeft) \
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V(MipsS32x4PackEven) \
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V(MipsS32x4PackOdd) \
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V(MipsS32x4InterleaveEven) \
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V(MipsS32x4InterleaveOdd) \
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V(MipsS32x4Shuffle) \
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V(MipsS16x8InterleaveRight) \
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V(MipsS16x8InterleaveLeft) \
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V(MipsS16x8PackEven) \
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V(MipsS16x8PackOdd) \
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V(MipsS16x8InterleaveEven) \
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V(MipsS16x8InterleaveOdd) \
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V(MipsS16x4Reverse) \
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V(MipsS16x2Reverse) \
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V(MipsS8x16InterleaveRight) \
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V(MipsS8x16InterleaveLeft) \
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V(MipsS8x16PackEven) \
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V(MipsS8x16PackOdd) \
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V(MipsS8x16InterleaveEven) \
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V(MipsS8x16InterleaveOdd) \
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V(MipsS8x16Shuffle) \
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V(MipsS8x16Concat) \
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V(MipsS8x8Reverse) \
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V(MipsS8x4Reverse) \
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V(MipsS8x2Reverse) \
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V(MipsMsaLd) \
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V(MipsMsaSt) \
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V(MipsI32x4SConvertI16x8Low) \
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V(MipsI32x4SConvertI16x8High) \
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V(MipsI32x4UConvertI16x8Low) \
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V(MipsI32x4UConvertI16x8High) \
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V(MipsI16x8SConvertI8x16Low) \
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V(MipsI16x8SConvertI8x16High) \
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V(MipsI16x8SConvertI32x4) \
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V(MipsI16x8UConvertI32x4) \
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V(MipsI16x8UConvertI8x16Low) \
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V(MipsI16x8UConvertI8x16High) \
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V(MipsI8x16SConvertI16x8) \
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V(MipsI8x16UConvertI16x8) \
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V(MipsWord32AtomicPairLoad) \
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V(MipsWord32AtomicPairStore) \
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V(MipsWord32AtomicPairAdd) \
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V(MipsWord32AtomicPairSub) \
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V(MipsWord32AtomicPairAnd) \
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V(MipsWord32AtomicPairOr) \
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V(MipsWord32AtomicPairXor) \
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V(MipsWord32AtomicPairExchange) \
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V(MipsWord32AtomicPairCompareExchange)
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// Addressing modes represent the "shape" of inputs to an instruction.
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// Many instructions support multiple addressing modes. Addressing modes
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// are encoded into the InstructionCode of the instruction and tell the
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// code generator after register allocation which assembler method to call.
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//
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// We use the following local notation for addressing modes:
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//
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// R = register
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// O = register or stack slot
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// D = double register
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// I = immediate (handle, external, int32)
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// MRI = [register + immediate]
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// MRR = [register + register]
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// TODO(plind): Add the new r6 address modes.
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#define TARGET_ADDRESSING_MODE_LIST(V) \
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V(MRI)
/* [%r0 + K] */
\
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V(MRR)
/* [%r0 + %r1] */
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}
// namespace compiler
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}
// namespace internal
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}
// namespace v8
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#endif // V8_COMPILER_BACKEND_MIPS_INSTRUCTION_CODES_MIPS_H_
v8
Definition:
libplatform.h:13
v8
src
compiler
backend
mips
instruction-codes-mips.h
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