V8 API Reference, 7.2.502.16 (for Deno 0.2.4)
disasm-mips64.cc
1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses.
8 //
9 // The example below will disassemble a block of code and print it to stdout.
10 //
11 // NameConverter converter;
12 // Disassembler d(converter);
13 // for (byte* pc = begin; pc < end;) {
14 // v8::internal::EmbeddedVector<char, 256> buffer;
15 // byte* prev_pc = pc;
16 // pc += d.InstructionDecode(buffer, pc);
17 // printf("%p %08x %s\n",
18 // prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer);
19 // }
20 //
21 // The Disassembler class also has a convenience method to disassemble a block
22 // of code into a FILE*, meaning that the above functionality could also be
23 // achieved by just calling Disassembler::Disassemble(stdout, begin, end);
24 
25 
26 #include <assert.h>
27 #include <stdarg.h>
28 #include <stdio.h>
29 #include <string.h>
30 
31 #if V8_TARGET_ARCH_MIPS64
32 
33 #include "src/base/platform/platform.h"
34 #include "src/disasm.h"
35 #include "src/macro-assembler.h"
36 #include "src/mips64/constants-mips64.h"
37 
38 namespace v8 {
39 namespace internal {
40 
41 //------------------------------------------------------------------------------
42 
43 // Decoder decodes and disassembles instructions into an output buffer.
44 // It uses the converter to convert register names and call destinations into
45 // more informative description.
46 class Decoder {
47  public:
48  Decoder(const disasm::NameConverter& converter,
49  v8::internal::Vector<char> out_buffer)
50  : converter_(converter),
51  out_buffer_(out_buffer),
52  out_buffer_pos_(0) {
53  out_buffer_[out_buffer_pos_] = '\0';
54  }
55 
56  ~Decoder() {}
57 
58  // Writes one disassembled instruction into 'buffer' (0-terminated).
59  // Returns the length of the disassembled machine instruction in bytes.
60  int InstructionDecode(byte* instruction);
61 
62  private:
63  // Bottleneck functions to print into the out_buffer.
64  void PrintChar(const char ch);
65  void Print(const char* str);
66 
67  // Printing of common values.
68  void PrintRegister(int reg);
69  void PrintFPURegister(int freg);
70  void PrintMSARegister(int wreg);
71  void PrintFPUStatusRegister(int freg);
72  void PrintMSAControlRegister(int creg);
73  void PrintRs(Instruction* instr);
74  void PrintRt(Instruction* instr);
75  void PrintRd(Instruction* instr);
76  void PrintFs(Instruction* instr);
77  void PrintFt(Instruction* instr);
78  void PrintFd(Instruction* instr);
79  void PrintSa(Instruction* instr);
80  void PrintLsaSa(Instruction* instr);
81  void PrintSd(Instruction* instr);
82  void PrintSs1(Instruction* instr);
83  void PrintSs2(Instruction* instr);
84  void PrintSs3(Instruction* instr);
85  void PrintSs4(Instruction* instr);
86  void PrintSs5(Instruction* instr);
87  void PrintBc(Instruction* instr);
88  void PrintCc(Instruction* instr);
89  void PrintFunction(Instruction* instr);
90  void PrintSecondaryField(Instruction* instr);
91  void PrintUImm9(Instruction* instr);
92  void PrintSImm9(Instruction* instr);
93  void PrintUImm16(Instruction* instr);
94  void PrintSImm16(Instruction* instr);
95  void PrintXImm16(Instruction* instr);
96  void PrintPCImm16(Instruction* instr, int delta_pc, int n_bits);
97  void PrintXImm18(Instruction* instr);
98  void PrintSImm18(Instruction* instr);
99  void PrintXImm19(Instruction* instr);
100  void PrintSImm19(Instruction* instr);
101  void PrintXImm21(Instruction* instr);
102  void PrintSImm21(Instruction* instr);
103  void PrintPCImm21(Instruction* instr, int delta_pc, int n_bits);
104  void PrintXImm26(Instruction* instr);
105  void PrintSImm26(Instruction* instr);
106  void PrintPCImm26(Instruction* instr, int delta_pc, int n_bits);
107  void PrintPCImm26(Instruction* instr);
108  void PrintCode(Instruction* instr); // For break and trap instructions.
109  void PrintFormat(Instruction* instr); // For floating format postfix.
110  void PrintBp2(Instruction* instr);
111  void PrintBp3(Instruction* instr);
112  void PrintMsaDataFormat(Instruction* instr);
113  void PrintMsaXImm8(Instruction* instr);
114  void PrintMsaImm8(Instruction* instr);
115  void PrintMsaImm5(Instruction* instr);
116  void PrintMsaSImm5(Instruction* instr);
117  void PrintMsaSImm10(Instruction* instr, bool is_mi10 = false);
118  void PrintMsaImmBit(Instruction* instr);
119  void PrintMsaImmElm(Instruction* instr);
120  void PrintMsaCopy(Instruction* instr);
121  // Printing of instruction name.
122  void PrintInstructionName(Instruction* instr);
123 
124  // Handle formatting of instructions and their options.
125  int FormatRegister(Instruction* instr, const char* option);
126  int FormatFPURegister(Instruction* instr, const char* option);
127  int FormatMSARegister(Instruction* instr, const char* option);
128  int FormatOption(Instruction* instr, const char* option);
129  void Format(Instruction* instr, const char* format);
130  void Unknown(Instruction* instr);
131  int DecodeBreakInstr(Instruction* instr);
132 
133  // Each of these functions decodes one particular instruction type.
134  bool DecodeTypeRegisterRsType(Instruction* instr);
135  void DecodeTypeRegisterSRsType(Instruction* instr);
136  void DecodeTypeRegisterDRsType(Instruction* instr);
137  void DecodeTypeRegisterLRsType(Instruction* instr);
138  void DecodeTypeRegisterWRsType(Instruction* instr);
139  void DecodeTypeRegisterSPECIAL(Instruction* instr);
140  void DecodeTypeRegisterSPECIAL2(Instruction* instr);
141  void DecodeTypeRegisterSPECIAL3(Instruction* instr);
142  void DecodeTypeRegisterCOP1(Instruction* instr);
143  void DecodeTypeRegisterCOP1X(Instruction* instr);
144  int DecodeTypeRegister(Instruction* instr);
145 
146  void DecodeTypeImmediateCOP1(Instruction* instr);
147  void DecodeTypeImmediateREGIMM(Instruction* instr);
148  void DecodeTypeImmediateSPECIAL3(Instruction* instr);
149  void DecodeTypeImmediate(Instruction* instr);
150 
151  void DecodeTypeJump(Instruction* instr);
152 
153  void DecodeTypeMsaI8(Instruction* instr);
154  void DecodeTypeMsaI5(Instruction* instr);
155  void DecodeTypeMsaI10(Instruction* instr);
156  void DecodeTypeMsaELM(Instruction* instr);
157  void DecodeTypeMsaBIT(Instruction* instr);
158  void DecodeTypeMsaMI10(Instruction* instr);
159  void DecodeTypeMsa3R(Instruction* instr);
160  void DecodeTypeMsa3RF(Instruction* instr);
161  void DecodeTypeMsaVec(Instruction* instr);
162  void DecodeTypeMsa2R(Instruction* instr);
163  void DecodeTypeMsa2RF(Instruction* instr);
164 
165  const disasm::NameConverter& converter_;
166  v8::internal::Vector<char> out_buffer_;
167  int out_buffer_pos_;
168 
169  DISALLOW_COPY_AND_ASSIGN(Decoder);
170 };
171 
172 
173 // Support for assertions in the Decoder formatting functions.
174 #define STRING_STARTS_WITH(string, compare_string) \
175  (strncmp(string, compare_string, strlen(compare_string)) == 0)
176 
177 
178 // Append the ch to the output buffer.
179 void Decoder::PrintChar(const char ch) {
180  out_buffer_[out_buffer_pos_++] = ch;
181 }
182 
183 
184 // Append the str to the output buffer.
185 void Decoder::Print(const char* str) {
186  char cur = *str++;
187  while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
188  PrintChar(cur);
189  cur = *str++;
190  }
191  out_buffer_[out_buffer_pos_] = 0;
192 }
193 
194 
195 // Print the register name according to the active name converter.
196 void Decoder::PrintRegister(int reg) {
197  Print(converter_.NameOfCPURegister(reg));
198 }
199 
200 
201 void Decoder::PrintRs(Instruction* instr) {
202  int reg = instr->RsValue();
203  PrintRegister(reg);
204 }
205 
206 
207 void Decoder::PrintRt(Instruction* instr) {
208  int reg = instr->RtValue();
209  PrintRegister(reg);
210 }
211 
212 
213 void Decoder::PrintRd(Instruction* instr) {
214  int reg = instr->RdValue();
215  PrintRegister(reg);
216 }
217 
218 
219 // Print the FPUregister name according to the active name converter.
220 void Decoder::PrintFPURegister(int freg) {
221  Print(converter_.NameOfXMMRegister(freg));
222 }
223 
224 void Decoder::PrintMSARegister(int wreg) { Print(MSARegisters::Name(wreg)); }
225 
226 void Decoder::PrintFPUStatusRegister(int freg) {
227  switch (freg) {
228  case kFCSRRegister:
229  Print("FCSR");
230  break;
231  default:
232  Print(converter_.NameOfXMMRegister(freg));
233  }
234 }
235 
236 void Decoder::PrintMSAControlRegister(int creg) {
237  switch (creg) {
238  case kMSAIRRegister:
239  Print("MSAIR");
240  break;
241  case kMSACSRRegister:
242  Print("MSACSR");
243  break;
244  default:
245  Print("no_msacreg");
246  }
247 }
248 
249 void Decoder::PrintFs(Instruction* instr) {
250  int freg = instr->RsValue();
251  PrintFPURegister(freg);
252 }
253 
254 
255 void Decoder::PrintFt(Instruction* instr) {
256  int freg = instr->RtValue();
257  PrintFPURegister(freg);
258 }
259 
260 
261 void Decoder::PrintFd(Instruction* instr) {
262  int freg = instr->RdValue();
263  PrintFPURegister(freg);
264 }
265 
266 
267 // Print the integer value of the sa field.
268 void Decoder::PrintSa(Instruction* instr) {
269  int sa = instr->SaValue();
270  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
271 }
272 
273 
274 // Print the integer value of the sa field of a lsa instruction.
275 void Decoder::PrintLsaSa(Instruction* instr) {
276  int sa = instr->LsaSaValue() + 1;
277  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
278 }
279 
280 
281 // Print the integer value of the rd field, when it is not used as reg.
282 void Decoder::PrintSd(Instruction* instr) {
283  int sd = instr->RdValue();
284  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd);
285 }
286 
287 // Print the integer value of ext/dext/dextu size from the msbd field.
288 void Decoder::PrintSs1(Instruction* instr) {
289  int msbd = instr->RdValue();
290  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", msbd + 1);
291 }
292 
293 // Print the integer value of ins/dins/dinsu size from the msb and lsb fields
294 // (for dinsu it is msbminus32 and lsbminus32 fields).
295 void Decoder::PrintSs2(Instruction* instr) {
296  int msb = instr->RdValue();
297  int lsb = instr->SaValue();
298  out_buffer_pos_ +=
299  SNPrintF(out_buffer_ + out_buffer_pos_, "%d", msb - lsb + 1);
300 }
301 
302 // Print the integer value of dextm size from the msbdminus32 field.
303 void Decoder::PrintSs3(Instruction* instr) {
304  int msbdminus32 = instr->RdValue();
305  out_buffer_pos_ +=
306  SNPrintF(out_buffer_ + out_buffer_pos_, "%d", msbdminus32 + 32 + 1);
307 }
308 
309 // Print the integer value of dinsm size from the msbminus32 and lsb fields.
310 void Decoder::PrintSs4(Instruction* instr) {
311  int msbminus32 = instr->RdValue();
312  int lsb = instr->SaValue();
313  out_buffer_pos_ +=
314  SNPrintF(out_buffer_ + out_buffer_pos_, "%d", msbminus32 + 32 - lsb + 1);
315 }
316 
317 // Print the integer value of dextu/dinsu pos from the lsbminus32 field.
318 void Decoder::PrintSs5(Instruction* instr) {
319  int lsbminus32 = instr->SaValue();
320  out_buffer_pos_ +=
321  SNPrintF(out_buffer_ + out_buffer_pos_, "%d", lsbminus32 + 32);
322 }
323 
324 
325 // Print the integer value of the cc field for the bc1t/f instructions.
326 void Decoder::PrintBc(Instruction* instr) {
327  int cc = instr->FBccValue();
328  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", cc);
329 }
330 
331 
332 // Print the integer value of the cc field for the FP compare instructions.
333 void Decoder::PrintCc(Instruction* instr) {
334  int cc = instr->FCccValue();
335  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "cc(%d)", cc);
336 }
337 
338 // Print 9-bit unsigned immediate value.
339 void Decoder::PrintUImm9(Instruction* instr) {
340  int32_t imm = instr->Imm9Value();
341  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
342 }
343 
344 // Print 9-bit signed immediate value.
345 void Decoder::PrintSImm9(Instruction* instr) {
346  int32_t imm = ((instr->Imm9Value()) << 23) >> 23;
347  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
348 }
349 
350 // Print 16-bit unsigned immediate value.
351 void Decoder::PrintUImm16(Instruction* instr) {
352  int32_t imm = instr->Imm16Value();
353  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
354 }
355 
356 
357 // Print 16-bit signed immediate value.
358 void Decoder::PrintSImm16(Instruction* instr) {
359  int32_t imm =
360  ((instr->Imm16Value()) << (32 - kImm16Bits)) >> (32 - kImm16Bits);
361  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
362 }
363 
364 
365 // Print 16-bit hexa immediate value.
366 void Decoder::PrintXImm16(Instruction* instr) {
367  int32_t imm = instr->Imm16Value();
368  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
369 }
370 
371 
372 // Print absoulte address for 16-bit offset or immediate value.
373 // The absolute address is calculated according following expression:
374 // PC + delta_pc + (offset << n_bits)
375 void Decoder::PrintPCImm16(Instruction* instr, int delta_pc, int n_bits) {
376  int16_t offset = instr->Imm16Value();
377  out_buffer_pos_ +=
378  SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
379  converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
380  delta_pc + (offset << n_bits)));
381 }
382 
383 
384 // Print 18-bit signed immediate value.
385 void Decoder::PrintSImm18(Instruction* instr) {
386  int32_t imm =
387  ((instr->Imm18Value()) << (32 - kImm18Bits)) >> (32 - kImm18Bits);
388  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
389 }
390 
391 
392 // Print 18-bit hexa immediate value.
393 void Decoder::PrintXImm18(Instruction* instr) {
394  int32_t imm = instr->Imm18Value();
395  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
396 }
397 
398 
399 // Print 19-bit hexa immediate value.
400 void Decoder::PrintXImm19(Instruction* instr) {
401  int32_t imm = instr->Imm19Value();
402  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
403 }
404 
405 
406 // Print 19-bit signed immediate value.
407 void Decoder::PrintSImm19(Instruction* instr) {
408  int32_t imm19 = instr->Imm19Value();
409  // set sign
410  imm19 <<= (32 - kImm19Bits);
411  imm19 >>= (32 - kImm19Bits);
412  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm19);
413 }
414 
415 
416 // Print 21-bit immediate value.
417 void Decoder::PrintXImm21(Instruction* instr) {
418  uint32_t imm = instr->Imm21Value();
419  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
420 }
421 
422 
423 // Print 21-bit signed immediate value.
424 void Decoder::PrintSImm21(Instruction* instr) {
425  int32_t imm21 = instr->Imm21Value();
426  // set sign
427  imm21 <<= (32 - kImm21Bits);
428  imm21 >>= (32 - kImm21Bits);
429  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm21);
430 }
431 
432 
433 // Print absoulte address for 21-bit offset or immediate value.
434 // The absolute address is calculated according following expression:
435 // PC + delta_pc + (offset << n_bits)
436 void Decoder::PrintPCImm21(Instruction* instr, int delta_pc, int n_bits) {
437  int32_t imm21 = instr->Imm21Value();
438  // set sign
439  imm21 <<= (32 - kImm21Bits);
440  imm21 >>= (32 - kImm21Bits);
441  out_buffer_pos_ +=
442  SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
443  converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
444  delta_pc + (imm21 << n_bits)));
445 }
446 
447 
448 // Print 26-bit hex immediate value.
449 void Decoder::PrintXImm26(Instruction* instr) {
450  uint64_t target = static_cast<uint64_t>(instr->Imm26Value())
451  << kImmFieldShift;
452  target = (reinterpret_cast<uint64_t>(instr) & ~0xFFFFFFF) | target;
453  out_buffer_pos_ +=
454  SNPrintF(out_buffer_ + out_buffer_pos_, "0x%" PRIx64, target);
455 }
456 
457 
458 // Print 26-bit signed immediate value.
459 void Decoder::PrintSImm26(Instruction* instr) {
460  int32_t imm26 = instr->Imm26Value();
461  // set sign
462  imm26 <<= (32 - kImm26Bits);
463  imm26 >>= (32 - kImm26Bits);
464  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm26);
465 }
466 
467 
468 // Print absoulte address for 26-bit offset or immediate value.
469 // The absolute address is calculated according following expression:
470 // PC + delta_pc + (offset << n_bits)
471 void Decoder::PrintPCImm26(Instruction* instr, int delta_pc, int n_bits) {
472  int32_t imm26 = instr->Imm26Value();
473  // set sign
474  imm26 <<= (32 - kImm26Bits);
475  imm26 >>= (32 - kImm26Bits);
476  out_buffer_pos_ +=
477  SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
478  converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
479  delta_pc + (imm26 << n_bits)));
480 }
481 
482 
483 // Print absoulte address for 26-bit offset or immediate value.
484 // The absolute address is calculated according following expression:
485 // PC[GPRLEN-1 .. 28] || instr_index26 || 00
486 void Decoder::PrintPCImm26(Instruction* instr) {
487  int32_t imm26 = instr->Imm26Value();
488  uint64_t pc_mask = ~0xFFFFFFF;
489  uint64_t pc = ((uint64_t)(instr + 1) & pc_mask) | (imm26 << 2);
490  out_buffer_pos_ +=
491  SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
492  converter_.NameOfAddress((reinterpret_cast<byte*>(pc))));
493 }
494 
495 
496 void Decoder::PrintBp2(Instruction* instr) {
497  int bp2 = instr->Bp2Value();
498  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", bp2);
499 }
500 
501 
502 void Decoder::PrintBp3(Instruction* instr) {
503  int bp3 = instr->Bp3Value();
504  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", bp3);
505 }
506 
507 
508 // Print 26-bit immediate value.
509 void Decoder::PrintCode(Instruction* instr) {
510  if (instr->OpcodeFieldRaw() != SPECIAL)
511  return; // Not a break or trap instruction.
512  switch (instr->FunctionFieldRaw()) {
513  case BREAK: {
514  int32_t code = instr->Bits(25, 6);
515  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
516  "0x%05x (%d)", code, code);
517  break;
518  }
519  case TGE:
520  case TGEU:
521  case TLT:
522  case TLTU:
523  case TEQ:
524  case TNE: {
525  int32_t code = instr->Bits(15, 6);
526  out_buffer_pos_ +=
527  SNPrintF(out_buffer_ + out_buffer_pos_, "0x%03x", code);
528  break;
529  }
530  default: // Not a break or trap instruction.
531  break;
532  }
533 }
534 
535 void Decoder::PrintMsaXImm8(Instruction* instr) {
536  int32_t imm = instr->MsaImm8Value();
537  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
538 }
539 
540 void Decoder::PrintMsaImm8(Instruction* instr) {
541  int32_t imm = instr->MsaImm8Value();
542  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
543 }
544 
545 void Decoder::PrintMsaImm5(Instruction* instr) {
546  int32_t imm = instr->MsaImm5Value();
547  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
548 }
549 
550 void Decoder::PrintMsaSImm5(Instruction* instr) {
551  int32_t imm = instr->MsaImm5Value();
552  imm <<= (32 - kMsaImm5Bits);
553  imm >>= (32 - kMsaImm5Bits);
554  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
555 }
556 
557 void Decoder::PrintMsaSImm10(Instruction* instr, bool is_mi10) {
558  int32_t imm = is_mi10 ? instr->MsaImmMI10Value() : instr->MsaImm10Value();
559  imm <<= (32 - kMsaImm10Bits);
560  imm >>= (32 - kMsaImm10Bits);
561  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
562 }
563 
564 void Decoder::PrintMsaImmBit(Instruction* instr) {
565  int32_t m = instr->MsaBitMValue();
566  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", m);
567 }
568 
569 void Decoder::PrintMsaImmElm(Instruction* instr) {
570  int32_t n = instr->MsaElmNValue();
571  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", n);
572 }
573 
574 void Decoder::PrintMsaCopy(Instruction* instr) {
575  int32_t rd = instr->WdValue();
576  int32_t ws = instr->WsValue();
577  int32_t n = instr->MsaElmNValue();
578  out_buffer_pos_ +=
579  SNPrintF(out_buffer_ + out_buffer_pos_, "%s, %s[%u]",
580  converter_.NameOfCPURegister(rd), MSARegisters::Name(ws), n);
581 }
582 
583 void Decoder::PrintFormat(Instruction* instr) {
584  char formatLetter = ' ';
585  switch (instr->RsFieldRaw()) {
586  case S:
587  formatLetter = 's';
588  break;
589  case D:
590  formatLetter = 'd';
591  break;
592  case W:
593  formatLetter = 'w';
594  break;
595  case L:
596  formatLetter = 'l';
597  break;
598  default:
599  UNREACHABLE();
600  break;
601  }
602  PrintChar(formatLetter);
603 }
604 
605 void Decoder::PrintMsaDataFormat(Instruction* instr) {
606  DCHECK(instr->IsMSAInstr());
607  char df = ' ';
608  if (instr->IsMSABranchInstr()) {
609  switch (instr->RsFieldRaw()) {
610  case BZ_V:
611  case BNZ_V:
612  df = 'v';
613  break;
614  case BZ_B:
615  case BNZ_B:
616  df = 'b';
617  break;
618  case BZ_H:
619  case BNZ_H:
620  df = 'h';
621  break;
622  case BZ_W:
623  case BNZ_W:
624  df = 'w';
625  break;
626  case BZ_D:
627  case BNZ_D:
628  df = 'd';
629  break;
630  default:
631  UNREACHABLE();
632  break;
633  }
634  } else {
635  char DF[] = {'b', 'h', 'w', 'd'};
636  switch (instr->MSAMinorOpcodeField()) {
637  case kMsaMinorI5:
638  case kMsaMinorI10:
639  case kMsaMinor3R:
640  df = DF[instr->Bits(22, 21)];
641  break;
642  case kMsaMinorMI10:
643  df = DF[instr->Bits(1, 0)];
644  break;
645  case kMsaMinorBIT:
646  df = DF[instr->MsaBitDf()];
647  break;
648  case kMsaMinorELM:
649  df = DF[instr->MsaElmDf()];
650  break;
651  case kMsaMinor3RF: {
652  uint32_t opcode = instr->InstructionBits() & kMsa3RFMask;
653  switch (opcode) {
654  case FEXDO:
655  case FTQ:
656  case MUL_Q:
657  case MADD_Q:
658  case MSUB_Q:
659  case MULR_Q:
660  case MADDR_Q:
661  case MSUBR_Q:
662  df = DF[1 + instr->Bit(21)];
663  break;
664  default:
665  df = DF[2 + instr->Bit(21)];
666  break;
667  }
668  } break;
669  case kMsaMinor2R:
670  df = DF[instr->Bits(17, 16)];
671  break;
672  case kMsaMinor2RF:
673  df = DF[2 + instr->Bit(16)];
674  break;
675  default:
676  UNREACHABLE();
677  break;
678  }
679  }
680 
681  PrintChar(df);
682 }
683 
684 // Printing of instruction name.
685 void Decoder::PrintInstructionName(Instruction* instr) {
686 }
687 
688 
689 // Handle all register based formatting in this function to reduce the
690 // complexity of FormatOption.
691 int Decoder::FormatRegister(Instruction* instr, const char* format) {
692  DCHECK_EQ(format[0], 'r');
693  if (format[1] == 's') { // 'rs: Rs register.
694  int reg = instr->RsValue();
695  PrintRegister(reg);
696  return 2;
697  } else if (format[1] == 't') { // 'rt: rt register.
698  int reg = instr->RtValue();
699  PrintRegister(reg);
700  return 2;
701  } else if (format[1] == 'd') { // 'rd: rd register.
702  int reg = instr->RdValue();
703  PrintRegister(reg);
704  return 2;
705  }
706  UNREACHABLE();
707 }
708 
709 
710 // Handle all FPUregister based formatting in this function to reduce the
711 // complexity of FormatOption.
712 int Decoder::FormatFPURegister(Instruction* instr, const char* format) {
713  DCHECK_EQ(format[0], 'f');
714  if ((CTC1 == instr->RsFieldRaw()) || (CFC1 == instr->RsFieldRaw())) {
715  if (format[1] == 's') { // 'fs: fs register.
716  int reg = instr->FsValue();
717  PrintFPUStatusRegister(reg);
718  return 2;
719  } else if (format[1] == 't') { // 'ft: ft register.
720  int reg = instr->FtValue();
721  PrintFPUStatusRegister(reg);
722  return 2;
723  } else if (format[1] == 'd') { // 'fd: fd register.
724  int reg = instr->FdValue();
725  PrintFPUStatusRegister(reg);
726  return 2;
727  } else if (format[1] == 'r') { // 'fr: fr register.
728  int reg = instr->FrValue();
729  PrintFPUStatusRegister(reg);
730  return 2;
731  }
732  } else {
733  if (format[1] == 's') { // 'fs: fs register.
734  int reg = instr->FsValue();
735  PrintFPURegister(reg);
736  return 2;
737  } else if (format[1] == 't') { // 'ft: ft register.
738  int reg = instr->FtValue();
739  PrintFPURegister(reg);
740  return 2;
741  } else if (format[1] == 'd') { // 'fd: fd register.
742  int reg = instr->FdValue();
743  PrintFPURegister(reg);
744  return 2;
745  } else if (format[1] == 'r') { // 'fr: fr register.
746  int reg = instr->FrValue();
747  PrintFPURegister(reg);
748  return 2;
749  }
750  }
751  UNREACHABLE();
752 }
753 
754 // Handle all MSARegister based formatting in this function to reduce the
755 // complexity of FormatOption.
756 int Decoder::FormatMSARegister(Instruction* instr, const char* format) {
757  DCHECK_EQ(format[0], 'w');
758  if (format[1] == 's') {
759  int reg = instr->WsValue();
760  PrintMSARegister(reg);
761  return 2;
762  } else if (format[1] == 't') {
763  int reg = instr->WtValue();
764  PrintMSARegister(reg);
765  return 2;
766  } else if (format[1] == 'd') {
767  int reg = instr->WdValue();
768  PrintMSARegister(reg);
769  return 2;
770  }
771 
772  UNREACHABLE();
773 }
774 
775 // FormatOption takes a formatting string and interprets it based on
776 // the current instructions. The format string points to the first
777 // character of the option string (the option escape has already been
778 // consumed by the caller.) FormatOption returns the number of
779 // characters that were consumed from the formatting string.
780 int Decoder::FormatOption(Instruction* instr, const char* format) {
781  switch (format[0]) {
782  case 'c': { // 'code for break or trap instructions.
783  DCHECK(STRING_STARTS_WITH(format, "code"));
784  PrintCode(instr);
785  return 4;
786  }
787  case 'i': { // 'imm16u or 'imm26.
788  if (format[3] == '1') {
789  if (format[4] == '6') {
790  DCHECK(STRING_STARTS_WITH(format, "imm16"));
791  switch (format[5]) {
792  case 's':
793  DCHECK(STRING_STARTS_WITH(format, "imm16s"));
794  PrintSImm16(instr);
795  break;
796  case 'u':
797  DCHECK(STRING_STARTS_WITH(format, "imm16u"));
798  PrintSImm16(instr);
799  break;
800  case 'x':
801  DCHECK(STRING_STARTS_WITH(format, "imm16x"));
802  PrintXImm16(instr);
803  break;
804  case 'p': { // The PC relative address.
805  DCHECK(STRING_STARTS_WITH(format, "imm16p"));
806  int delta_pc = 0;
807  int n_bits = 0;
808  switch (format[6]) {
809  case '4': {
810  DCHECK(STRING_STARTS_WITH(format, "imm16p4"));
811  delta_pc = 4;
812  switch (format[8]) {
813  case '2':
814  DCHECK(STRING_STARTS_WITH(format, "imm16p4s2"));
815  n_bits = 2;
816  PrintPCImm16(instr, delta_pc, n_bits);
817  return 9;
818  }
819  }
820  }
821  }
822  }
823  return 6;
824  } else if (format[4] == '8') {
825  DCHECK(STRING_STARTS_WITH(format, "imm18"));
826  switch (format[5]) {
827  case 's':
828  DCHECK(STRING_STARTS_WITH(format, "imm18s"));
829  PrintSImm18(instr);
830  break;
831  case 'x':
832  DCHECK(STRING_STARTS_WITH(format, "imm18x"));
833  PrintXImm18(instr);
834  break;
835  }
836  return 6;
837  } else if (format[4] == '9') {
838  DCHECK(STRING_STARTS_WITH(format, "imm19"));
839  switch (format[5]) {
840  case 's':
841  DCHECK(STRING_STARTS_WITH(format, "imm19s"));
842  PrintSImm19(instr);
843  break;
844  case 'x':
845  DCHECK(STRING_STARTS_WITH(format, "imm19x"));
846  PrintXImm19(instr);
847  break;
848  }
849  return 6;
850  } else if (format[4] == '0' && format[5] == 's') {
851  DCHECK(STRING_STARTS_WITH(format, "imm10s"));
852  if (format[6] == '1') {
853  DCHECK(STRING_STARTS_WITH(format, "imm10s1"));
854  PrintMsaSImm10(instr, false);
855  } else if (format[6] == '2') {
856  DCHECK(STRING_STARTS_WITH(format, "imm10s2"));
857  PrintMsaSImm10(instr, true);
858  }
859  return 7;
860  }
861  } else if (format[3] == '2' && format[4] == '1') {
862  DCHECK(STRING_STARTS_WITH(format, "imm21"));
863  switch (format[5]) {
864  case 's':
865  DCHECK(STRING_STARTS_WITH(format, "imm21s"));
866  PrintSImm21(instr);
867  break;
868  case 'x':
869  DCHECK(STRING_STARTS_WITH(format, "imm21x"));
870  PrintXImm21(instr);
871  break;
872  case 'p': { // The PC relative address.
873  DCHECK(STRING_STARTS_WITH(format, "imm21p"));
874  int delta_pc = 0;
875  int n_bits = 0;
876  switch (format[6]) {
877  case '4': {
878  DCHECK(STRING_STARTS_WITH(format, "imm21p4"));
879  delta_pc = 4;
880  switch (format[8]) {
881  case '2':
882  DCHECK(STRING_STARTS_WITH(format, "imm21p4s2"));
883  n_bits = 2;
884  PrintPCImm21(instr, delta_pc, n_bits);
885  return 9;
886  }
887  }
888  }
889  }
890  }
891  return 6;
892  } else if (format[3] == '2' && format[4] == '6') {
893  DCHECK(STRING_STARTS_WITH(format, "imm26"));
894  switch (format[5]) {
895  case 's':
896  DCHECK(STRING_STARTS_WITH(format, "imm26s"));
897  PrintSImm26(instr);
898  break;
899  case 'x':
900  DCHECK(STRING_STARTS_WITH(format, "imm26x"));
901  PrintXImm26(instr);
902  break;
903  case 'p': { // The PC relative address.
904  DCHECK(STRING_STARTS_WITH(format, "imm26p"));
905  int delta_pc = 0;
906  int n_bits = 0;
907  switch (format[6]) {
908  case '4': {
909  DCHECK(STRING_STARTS_WITH(format, "imm26p4"));
910  delta_pc = 4;
911  switch (format[8]) {
912  case '2':
913  DCHECK(STRING_STARTS_WITH(format, "imm26p4s2"));
914  n_bits = 2;
915  PrintPCImm26(instr, delta_pc, n_bits);
916  return 9;
917  }
918  }
919  }
920  }
921  case 'j': { // Absolute address for jump instructions.
922  DCHECK(STRING_STARTS_WITH(format, "imm26j"));
923  PrintPCImm26(instr);
924  break;
925  }
926  }
927  return 6;
928  } else if (format[3] == '5') {
929  DCHECK(STRING_STARTS_WITH(format, "imm5"));
930  if (format[4] == 'u') {
931  DCHECK(STRING_STARTS_WITH(format, "imm5u"));
932  PrintMsaImm5(instr);
933  } else if (format[4] == 's') {
934  DCHECK(STRING_STARTS_WITH(format, "imm5s"));
935  PrintMsaSImm5(instr);
936  }
937  return 5;
938  } else if (format[3] == '8') {
939  DCHECK(STRING_STARTS_WITH(format, "imm8"));
940  PrintMsaImm8(instr);
941  return 4;
942  } else if (format[3] == '9') {
943  DCHECK(STRING_STARTS_WITH(format, "imm9"));
944  if (format[4] == 'u') {
945  DCHECK(STRING_STARTS_WITH(format, "imm9u"));
946  PrintUImm9(instr);
947  } else if (format[4] == 's') {
948  DCHECK(STRING_STARTS_WITH(format, "imm9s"));
949  PrintSImm9(instr);
950  }
951  return 5;
952  } else if (format[3] == 'b') {
953  DCHECK(STRING_STARTS_WITH(format, "immb"));
954  PrintMsaImmBit(instr);
955  return 4;
956  } else if (format[3] == 'e') {
957  DCHECK(STRING_STARTS_WITH(format, "imme"));
958  PrintMsaImmElm(instr);
959  return 4;
960  }
961  UNREACHABLE();
962  }
963  case 'r': { // 'r: registers.
964  return FormatRegister(instr, format);
965  }
966  case 'f': { // 'f: FPUregisters.
967  return FormatFPURegister(instr, format);
968  }
969  case 'w': { // 'w: MSA Register
970  return FormatMSARegister(instr, format);
971  }
972  case 's': { // 'sa.
973  switch (format[1]) {
974  case 'a':
975  if (format[2] == '2') {
976  DCHECK(STRING_STARTS_WITH(format, "sa2")); // 'sa2
977  PrintLsaSa(instr);
978  return 3;
979  } else {
980  DCHECK(STRING_STARTS_WITH(format, "sa"));
981  PrintSa(instr);
982  return 2;
983  }
984  break;
985  case 'd': {
986  DCHECK(STRING_STARTS_WITH(format, "sd"));
987  PrintSd(instr);
988  return 2;
989  }
990  case 's': {
991  if (format[2] == '1') {
992  DCHECK(STRING_STARTS_WITH(format, "ss1")); // ext, dext, dextu size
993  PrintSs1(instr);
994  } else if (format[2] == '2') {
995  DCHECK(STRING_STARTS_WITH(format, "ss2")); // ins, dins, dinsu size
996  PrintSs2(instr);
997  } else if (format[2] == '3') {
998  DCHECK(STRING_STARTS_WITH(format, "ss3")); // dextm size
999  PrintSs3(instr);
1000  } else if (format[2] == '4') {
1001  DCHECK(STRING_STARTS_WITH(format, "ss4")); // dinsm size
1002  PrintSs4(instr);
1003  } else {
1004  DCHECK(STRING_STARTS_WITH(format, "ss5")); // dextu, dinsu pos
1005  PrintSs5(instr);
1006  }
1007  return 3;
1008  }
1009  }
1010  }
1011  case 'b': {
1012  switch (format[1]) {
1013  case 'c': { // 'bc - Special for bc1 cc field.
1014  DCHECK(STRING_STARTS_WITH(format, "bc"));
1015  PrintBc(instr);
1016  return 2;
1017  }
1018  case 'p': {
1019  switch (format[2]) {
1020  case '2': { // 'bp2
1021  DCHECK(STRING_STARTS_WITH(format, "bp2"));
1022  PrintBp2(instr);
1023  return 3;
1024  }
1025  case '3': { // 'bp3
1026  DCHECK(STRING_STARTS_WITH(format, "bp3"));
1027  PrintBp3(instr);
1028  return 3;
1029  }
1030  }
1031  }
1032  }
1033  }
1034  case 'C': { // 'Cc - Special for c.xx.d cc field.
1035  DCHECK(STRING_STARTS_WITH(format, "Cc"));
1036  PrintCc(instr);
1037  return 2;
1038  }
1039  case 't':
1040  if (instr->IsMSAInstr()) {
1041  PrintMsaDataFormat(instr);
1042  } else {
1043  PrintFormat(instr);
1044  }
1045  return 1;
1046  }
1047  UNREACHABLE();
1048 }
1049 
1050 
1051 // Format takes a formatting string for a whole instruction and prints it into
1052 // the output buffer. All escaped options are handed to FormatOption to be
1053 // parsed further.
1054 void Decoder::Format(Instruction* instr, const char* format) {
1055  char cur = *format++;
1056  while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
1057  if (cur == '\'') { // Single quote is used as the formatting escape.
1058  format += FormatOption(instr, format);
1059  } else {
1060  out_buffer_[out_buffer_pos_++] = cur;
1061  }
1062  cur = *format++;
1063  }
1064  out_buffer_[out_buffer_pos_] = '\0';
1065 }
1066 
1067 
1068 // For currently unimplemented decodings the disassembler calls Unknown(instr)
1069 // which will just print "unknown" of the instruction bits.
1070 void Decoder::Unknown(Instruction* instr) {
1071  Format(instr, "unknown");
1072 }
1073 
1074 
1075 int Decoder::DecodeBreakInstr(Instruction* instr) {
1076  // This is already known to be BREAK instr, just extract the code.
1077  if (instr->Bits(25, 6) == static_cast<int>(kMaxStopCode)) {
1078  // This is stop(msg).
1079  Format(instr, "break, code: 'code");
1080  out_buffer_pos_ += SNPrintF(
1081  out_buffer_ + out_buffer_pos_, "\n%p %08" PRIx64,
1082  static_cast<void*>(reinterpret_cast<int32_t*>(instr + kInstrSize)),
1083  reinterpret_cast<uint64_t>(
1084  *reinterpret_cast<char**>(instr + kInstrSize)));
1085  // Size 3: the break_ instr, plus embedded 64-bit char pointer.
1086  return 3 * kInstrSize;
1087  } else {
1088  Format(instr, "break, code: 'code");
1089  return kInstrSize;
1090  }
1091 }
1092 
1093 
1094 bool Decoder::DecodeTypeRegisterRsType(Instruction* instr) {
1095  switch (instr->FunctionFieldRaw()) {
1096  case RINT:
1097  Format(instr, "rint.'t 'fd, 'fs");
1098  break;
1099  case SEL:
1100  Format(instr, "sel.'t 'fd, 'fs, 'ft");
1101  break;
1102  case SELEQZ_C:
1103  Format(instr, "seleqz.'t 'fd, 'fs, 'ft");
1104  break;
1105  case SELNEZ_C:
1106  Format(instr, "selnez.'t 'fd, 'fs, 'ft");
1107  break;
1108  case MOVZ_C:
1109  Format(instr, "movz.'t 'fd, 'fs, 'rt");
1110  break;
1111  case MOVN_C:
1112  Format(instr, "movn.'t 'fd, 'fs, 'rt");
1113  break;
1114  case MOVF:
1115  if (instr->Bit(16)) {
1116  Format(instr, "movt.'t 'fd, 'fs, 'Cc");
1117  } else {
1118  Format(instr, "movf.'t 'fd, 'fs, 'Cc");
1119  }
1120  break;
1121  case MIN:
1122  Format(instr, "min.'t 'fd, 'fs, 'ft");
1123  break;
1124  case MAX:
1125  Format(instr, "max.'t 'fd, 'fs, 'ft");
1126  break;
1127  case MINA:
1128  Format(instr, "mina.'t 'fd, 'fs, 'ft");
1129  break;
1130  case MAXA:
1131  Format(instr, "maxa.'t 'fd, 'fs, 'ft");
1132  break;
1133  case ADD_D:
1134  Format(instr, "add.'t 'fd, 'fs, 'ft");
1135  break;
1136  case SUB_D:
1137  Format(instr, "sub.'t 'fd, 'fs, 'ft");
1138  break;
1139  case MUL_D:
1140  Format(instr, "mul.'t 'fd, 'fs, 'ft");
1141  break;
1142  case DIV_D:
1143  Format(instr, "div.'t 'fd, 'fs, 'ft");
1144  break;
1145  case ABS_D:
1146  Format(instr, "abs.'t 'fd, 'fs");
1147  break;
1148  case MOV_D:
1149  Format(instr, "mov.'t 'fd, 'fs");
1150  break;
1151  case NEG_D:
1152  Format(instr, "neg.'t 'fd, 'fs");
1153  break;
1154  case SQRT_D:
1155  Format(instr, "sqrt.'t 'fd, 'fs");
1156  break;
1157  case RECIP_D:
1158  Format(instr, "recip.'t 'fd, 'fs");
1159  break;
1160  case RSQRT_D:
1161  Format(instr, "rsqrt.'t 'fd, 'fs");
1162  break;
1163  case CVT_W_D:
1164  Format(instr, "cvt.w.'t 'fd, 'fs");
1165  break;
1166  case CVT_L_D:
1167  Format(instr, "cvt.l.'t 'fd, 'fs");
1168  break;
1169  case TRUNC_W_D:
1170  Format(instr, "trunc.w.'t 'fd, 'fs");
1171  break;
1172  case TRUNC_L_D:
1173  Format(instr, "trunc.l.'t 'fd, 'fs");
1174  break;
1175  case ROUND_W_D:
1176  Format(instr, "round.w.'t 'fd, 'fs");
1177  break;
1178  case ROUND_L_D:
1179  Format(instr, "round.l.'t 'fd, 'fs");
1180  break;
1181  case FLOOR_W_D:
1182  Format(instr, "floor.w.'t 'fd, 'fs");
1183  break;
1184  case FLOOR_L_D:
1185  Format(instr, "floor.l.'t 'fd, 'fs");
1186  break;
1187  case CEIL_W_D:
1188  Format(instr, "ceil.w.'t 'fd, 'fs");
1189  break;
1190  case CEIL_L_D:
1191  Format(instr, "ceil.l.'t 'fd, 'fs");
1192  break;
1193  case CLASS_D:
1194  Format(instr, "class.'t 'fd, 'fs");
1195  break;
1196  case CVT_S_D:
1197  Format(instr, "cvt.s.'t 'fd, 'fs");
1198  break;
1199  case C_F_D:
1200  Format(instr, "c.f.'t 'fs, 'ft, 'Cc");
1201  break;
1202  case C_UN_D:
1203  Format(instr, "c.un.'t 'fs, 'ft, 'Cc");
1204  break;
1205  case C_EQ_D:
1206  Format(instr, "c.eq.'t 'fs, 'ft, 'Cc");
1207  break;
1208  case C_UEQ_D:
1209  Format(instr, "c.ueq.'t 'fs, 'ft, 'Cc");
1210  break;
1211  case C_OLT_D:
1212  Format(instr, "c.olt.'t 'fs, 'ft, 'Cc");
1213  break;
1214  case C_ULT_D:
1215  Format(instr, "c.ult.'t 'fs, 'ft, 'Cc");
1216  break;
1217  case C_OLE_D:
1218  Format(instr, "c.ole.'t 'fs, 'ft, 'Cc");
1219  break;
1220  case C_ULE_D:
1221  Format(instr, "c.ule.'t 'fs, 'ft, 'Cc");
1222  break;
1223  default:
1224  return false;
1225  }
1226  return true;
1227 }
1228 
1229 
1230 void Decoder::DecodeTypeRegisterSRsType(Instruction* instr) {
1231  if (!DecodeTypeRegisterRsType(instr)) {
1232  switch (instr->FunctionFieldRaw()) {
1233  case CVT_D_S:
1234  Format(instr, "cvt.d.'t 'fd, 'fs");
1235  break;
1236  case MADDF_S:
1237  Format(instr, "maddf.s 'fd, 'fs, 'ft");
1238  break;
1239  case MSUBF_S:
1240  Format(instr, "msubf.s 'fd, 'fs, 'ft");
1241  break;
1242  default:
1243  Format(instr, "unknown.cop1.'t");
1244  break;
1245  }
1246  }
1247 }
1248 
1249 
1250 void Decoder::DecodeTypeRegisterDRsType(Instruction* instr) {
1251  if (!DecodeTypeRegisterRsType(instr)) {
1252  switch (instr->FunctionFieldRaw()) {
1253  case MADDF_D:
1254  Format(instr, "maddf.d 'fd, 'fs, 'ft");
1255  break;
1256  case MSUBF_D:
1257  Format(instr, "msubf.d 'fd, 'fs, 'ft");
1258  break;
1259  default:
1260  Format(instr, "unknown.cop1.'t");
1261  break;
1262  }
1263  }
1264 }
1265 
1266 
1267 void Decoder::DecodeTypeRegisterLRsType(Instruction* instr) {
1268  switch (instr->FunctionFieldRaw()) {
1269  case CVT_D_L:
1270  Format(instr, "cvt.d.l 'fd, 'fs");
1271  break;
1272  case CVT_S_L:
1273  Format(instr, "cvt.s.l 'fd, 'fs");
1274  break;
1275  case CMP_AF:
1276  Format(instr, "cmp.af.d 'fd, 'fs, 'ft");
1277  break;
1278  case CMP_UN:
1279  Format(instr, "cmp.un.d 'fd, 'fs, 'ft");
1280  break;
1281  case CMP_EQ:
1282  Format(instr, "cmp.eq.d 'fd, 'fs, 'ft");
1283  break;
1284  case CMP_UEQ:
1285  Format(instr, "cmp.ueq.d 'fd, 'fs, 'ft");
1286  break;
1287  case CMP_LT:
1288  Format(instr, "cmp.lt.d 'fd, 'fs, 'ft");
1289  break;
1290  case CMP_ULT:
1291  Format(instr, "cmp.ult.d 'fd, 'fs, 'ft");
1292  break;
1293  case CMP_LE:
1294  Format(instr, "cmp.le.d 'fd, 'fs, 'ft");
1295  break;
1296  case CMP_ULE:
1297  Format(instr, "cmp.ule.d 'fd, 'fs, 'ft");
1298  break;
1299  case CMP_OR:
1300  Format(instr, "cmp.or.d 'fd, 'fs, 'ft");
1301  break;
1302  case CMP_UNE:
1303  Format(instr, "cmp.une.d 'fd, 'fs, 'ft");
1304  break;
1305  case CMP_NE:
1306  Format(instr, "cmp.ne.d 'fd, 'fs, 'ft");
1307  break;
1308  default:
1309  UNREACHABLE();
1310  }
1311 }
1312 
1313 
1314 void Decoder::DecodeTypeRegisterWRsType(Instruction* instr) {
1315  switch (instr->FunctionValue()) {
1316  case CVT_S_W: // Convert word to float (single).
1317  Format(instr, "cvt.s.w 'fd, 'fs");
1318  break;
1319  case CVT_D_W: // Convert word to double.
1320  Format(instr, "cvt.d.w 'fd, 'fs");
1321  break;
1322  case CMP_AF:
1323  Format(instr, "cmp.af.s 'fd, 'fs, 'ft");
1324  break;
1325  case CMP_UN:
1326  Format(instr, "cmp.un.s 'fd, 'fs, 'ft");
1327  break;
1328  case CMP_EQ:
1329  Format(instr, "cmp.eq.s 'fd, 'fs, 'ft");
1330  break;
1331  case CMP_UEQ:
1332  Format(instr, "cmp.ueq.s 'fd, 'fs, 'ft");
1333  break;
1334  case CMP_LT:
1335  Format(instr, "cmp.lt.s 'fd, 'fs, 'ft");
1336  break;
1337  case CMP_ULT:
1338  Format(instr, "cmp.ult.s 'fd, 'fs, 'ft");
1339  break;
1340  case CMP_LE:
1341  Format(instr, "cmp.le.s 'fd, 'fs, 'ft");
1342  break;
1343  case CMP_ULE:
1344  Format(instr, "cmp.ule.s 'fd, 'fs, 'ft");
1345  break;
1346  case CMP_OR:
1347  Format(instr, "cmp.or.s 'fd, 'fs, 'ft");
1348  break;
1349  case CMP_UNE:
1350  Format(instr, "cmp.une.s 'fd, 'fs, 'ft");
1351  break;
1352  case CMP_NE:
1353  Format(instr, "cmp.ne.s 'fd, 'fs, 'ft");
1354  break;
1355  default:
1356  UNREACHABLE();
1357  }
1358 }
1359 
1360 
1361 void Decoder::DecodeTypeRegisterCOP1(Instruction* instr) {
1362  switch (instr->RsFieldRaw()) {
1363  case MFC1:
1364  Format(instr, "mfc1 'rt, 'fs");
1365  break;
1366  case DMFC1:
1367  Format(instr, "dmfc1 'rt, 'fs");
1368  break;
1369  case MFHC1:
1370  Format(instr, "mfhc1 'rt, 'fs");
1371  break;
1372  case MTC1:
1373  Format(instr, "mtc1 'rt, 'fs");
1374  break;
1375  case DMTC1:
1376  Format(instr, "dmtc1 'rt, 'fs");
1377  break;
1378  // These are called "fs" too, although they are not FPU registers.
1379  case CTC1:
1380  Format(instr, "ctc1 'rt, 'fs");
1381  break;
1382  case CFC1:
1383  Format(instr, "cfc1 'rt, 'fs");
1384  break;
1385  case MTHC1:
1386  Format(instr, "mthc1 'rt, 'fs");
1387  break;
1388  case S:
1389  DecodeTypeRegisterSRsType(instr);
1390  break;
1391  case D:
1392  DecodeTypeRegisterDRsType(instr);
1393  break;
1394  case W:
1395  DecodeTypeRegisterWRsType(instr);
1396  break;
1397  case L:
1398  DecodeTypeRegisterLRsType(instr);
1399  break;
1400  default:
1401  UNREACHABLE();
1402  }
1403 }
1404 
1405 
1406 void Decoder::DecodeTypeRegisterCOP1X(Instruction* instr) {
1407  switch (instr->FunctionFieldRaw()) {
1408  case MADD_S:
1409  Format(instr, "madd.s 'fd, 'fr, 'fs, 'ft");
1410  break;
1411  case MADD_D:
1412  Format(instr, "madd.d 'fd, 'fr, 'fs, 'ft");
1413  break;
1414  case MSUB_S:
1415  Format(instr, "msub.s 'fd, 'fr, 'fs, 'ft");
1416  break;
1417  case MSUB_D:
1418  Format(instr, "msub.d 'fd, 'fr, 'fs, 'ft");
1419  break;
1420  default:
1421  UNREACHABLE();
1422  }
1423 }
1424 
1425 
1426 void Decoder::DecodeTypeRegisterSPECIAL(Instruction* instr) {
1427  switch (instr->FunctionFieldRaw()) {
1428  case JR:
1429  Format(instr, "jr 'rs");
1430  break;
1431  case JALR:
1432  Format(instr, "jalr 'rs, 'rd");
1433  break;
1434  case SLL:
1435  if (0x0 == static_cast<int>(instr->InstructionBits()))
1436  Format(instr, "nop");
1437  else
1438  Format(instr, "sll 'rd, 'rt, 'sa");
1439  break;
1440  case DSLL:
1441  Format(instr, "dsll 'rd, 'rt, 'sa");
1442  break;
1443  case D_MUL_MUH: // Equals to DMUL.
1444  if (kArchVariant != kMips64r6) {
1445  Format(instr, "dmult 'rs, 'rt");
1446  } else {
1447  if (instr->SaValue() == MUL_OP) {
1448  Format(instr, "dmul 'rd, 'rs, 'rt");
1449  } else {
1450  Format(instr, "dmuh 'rd, 'rs, 'rt");
1451  }
1452  }
1453  break;
1454  case DSLL32:
1455  Format(instr, "dsll32 'rd, 'rt, 'sa");
1456  break;
1457  case SRL:
1458  if (instr->RsValue() == 0) {
1459  Format(instr, "srl 'rd, 'rt, 'sa");
1460  } else {
1461  Format(instr, "rotr 'rd, 'rt, 'sa");
1462  }
1463  break;
1464  case DSRL:
1465  if (instr->RsValue() == 0) {
1466  Format(instr, "dsrl 'rd, 'rt, 'sa");
1467  } else {
1468  Format(instr, "drotr 'rd, 'rt, 'sa");
1469  }
1470  break;
1471  case DSRL32:
1472  if (instr->RsValue() == 0) {
1473  Format(instr, "dsrl32 'rd, 'rt, 'sa");
1474  } else {
1475  Format(instr, "drotr32 'rd, 'rt, 'sa");
1476  }
1477  break;
1478  case SRA:
1479  Format(instr, "sra 'rd, 'rt, 'sa");
1480  break;
1481  case DSRA:
1482  Format(instr, "dsra 'rd, 'rt, 'sa");
1483  break;
1484  case DSRA32:
1485  Format(instr, "dsra32 'rd, 'rt, 'sa");
1486  break;
1487  case SLLV:
1488  Format(instr, "sllv 'rd, 'rt, 'rs");
1489  break;
1490  case DSLLV:
1491  Format(instr, "dsllv 'rd, 'rt, 'rs");
1492  break;
1493  case SRLV:
1494  if (instr->SaValue() == 0) {
1495  Format(instr, "srlv 'rd, 'rt, 'rs");
1496  } else {
1497  Format(instr, "rotrv 'rd, 'rt, 'rs");
1498  }
1499  break;
1500  case DSRLV:
1501  if (instr->SaValue() == 0) {
1502  Format(instr, "dsrlv 'rd, 'rt, 'rs");
1503  } else {
1504  Format(instr, "drotrv 'rd, 'rt, 'rs");
1505  }
1506  break;
1507  case SRAV:
1508  Format(instr, "srav 'rd, 'rt, 'rs");
1509  break;
1510  case DSRAV:
1511  Format(instr, "dsrav 'rd, 'rt, 'rs");
1512  break;
1513  case LSA:
1514  Format(instr, "lsa 'rd, 'rt, 'rs, 'sa2");
1515  break;
1516  case DLSA:
1517  Format(instr, "dlsa 'rd, 'rt, 'rs, 'sa2");
1518  break;
1519  case MFHI:
1520  if (instr->Bits(25, 16) == 0) {
1521  Format(instr, "mfhi 'rd");
1522  } else {
1523  if ((instr->FunctionFieldRaw() == CLZ_R6) && (instr->FdValue() == 1)) {
1524  Format(instr, "clz 'rd, 'rs");
1525  } else if ((instr->FunctionFieldRaw() == CLO_R6) &&
1526  (instr->FdValue() == 1)) {
1527  Format(instr, "clo 'rd, 'rs");
1528  }
1529  }
1530  break;
1531  case MFLO:
1532  if (instr->Bits(25, 16) == 0) {
1533  Format(instr, "mflo 'rd");
1534  } else {
1535  if ((instr->FunctionFieldRaw() == DCLZ_R6) && (instr->FdValue() == 1)) {
1536  Format(instr, "dclz 'rd, 'rs");
1537  } else if ((instr->FunctionFieldRaw() == DCLO_R6) &&
1538  (instr->FdValue() == 1)) {
1539  Format(instr, "dclo 'rd, 'rs");
1540  }
1541  }
1542  break;
1543  case D_MUL_MUH_U: // Equals to DMULTU.
1544  if (kArchVariant != kMips64r6) {
1545  Format(instr, "dmultu 'rs, 'rt");
1546  } else {
1547  if (instr->SaValue() == MUL_OP) {
1548  Format(instr, "dmulu 'rd, 'rs, 'rt");
1549  } else {
1550  Format(instr, "dmuhu 'rd, 'rs, 'rt");
1551  }
1552  }
1553  break;
1554  case MULT: // @Mips64r6 == MUL_MUH.
1555  if (kArchVariant != kMips64r6) {
1556  Format(instr, "mult 'rs, 'rt");
1557  } else {
1558  if (instr->SaValue() == MUL_OP) {
1559  Format(instr, "mul 'rd, 'rs, 'rt");
1560  } else {
1561  Format(instr, "muh 'rd, 'rs, 'rt");
1562  }
1563  }
1564  break;
1565  case MULTU: // @Mips64r6 == MUL_MUH_U.
1566  if (kArchVariant != kMips64r6) {
1567  Format(instr, "multu 'rs, 'rt");
1568  } else {
1569  if (instr->SaValue() == MUL_OP) {
1570  Format(instr, "mulu 'rd, 'rs, 'rt");
1571  } else {
1572  Format(instr, "muhu 'rd, 'rs, 'rt");
1573  }
1574  }
1575 
1576  break;
1577  case DIV: // @Mips64r6 == DIV_MOD.
1578  if (kArchVariant != kMips64r6) {
1579  Format(instr, "div 'rs, 'rt");
1580  } else {
1581  if (instr->SaValue() == DIV_OP) {
1582  Format(instr, "div 'rd, 'rs, 'rt");
1583  } else {
1584  Format(instr, "mod 'rd, 'rs, 'rt");
1585  }
1586  }
1587  break;
1588  case DDIV: // @Mips64r6 == D_DIV_MOD.
1589  if (kArchVariant != kMips64r6) {
1590  Format(instr, "ddiv 'rs, 'rt");
1591  } else {
1592  if (instr->SaValue() == DIV_OP) {
1593  Format(instr, "ddiv 'rd, 'rs, 'rt");
1594  } else {
1595  Format(instr, "dmod 'rd, 'rs, 'rt");
1596  }
1597  }
1598  break;
1599  case DIVU: // @Mips64r6 == DIV_MOD_U.
1600  if (kArchVariant != kMips64r6) {
1601  Format(instr, "divu 'rs, 'rt");
1602  } else {
1603  if (instr->SaValue() == DIV_OP) {
1604  Format(instr, "divu 'rd, 'rs, 'rt");
1605  } else {
1606  Format(instr, "modu 'rd, 'rs, 'rt");
1607  }
1608  }
1609  break;
1610  case DDIVU: // @Mips64r6 == D_DIV_MOD_U.
1611  if (kArchVariant != kMips64r6) {
1612  Format(instr, "ddivu 'rs, 'rt");
1613  } else {
1614  if (instr->SaValue() == DIV_OP) {
1615  Format(instr, "ddivu 'rd, 'rs, 'rt");
1616  } else {
1617  Format(instr, "dmodu 'rd, 'rs, 'rt");
1618  }
1619  }
1620  break;
1621  case ADD:
1622  Format(instr, "add 'rd, 'rs, 'rt");
1623  break;
1624  case DADD:
1625  Format(instr, "dadd 'rd, 'rs, 'rt");
1626  break;
1627  case ADDU:
1628  Format(instr, "addu 'rd, 'rs, 'rt");
1629  break;
1630  case DADDU:
1631  Format(instr, "daddu 'rd, 'rs, 'rt");
1632  break;
1633  case SUB:
1634  Format(instr, "sub 'rd, 'rs, 'rt");
1635  break;
1636  case DSUB:
1637  Format(instr, "dsub 'rd, 'rs, 'rt");
1638  break;
1639  case SUBU:
1640  Format(instr, "subu 'rd, 'rs, 'rt");
1641  break;
1642  case DSUBU:
1643  Format(instr, "dsubu 'rd, 'rs, 'rt");
1644  break;
1645  case AND:
1646  Format(instr, "and 'rd, 'rs, 'rt");
1647  break;
1648  case OR:
1649  if (0 == instr->RsValue()) {
1650  Format(instr, "mov 'rd, 'rt");
1651  } else if (0 == instr->RtValue()) {
1652  Format(instr, "mov 'rd, 'rs");
1653  } else {
1654  Format(instr, "or 'rd, 'rs, 'rt");
1655  }
1656  break;
1657  case XOR:
1658  Format(instr, "xor 'rd, 'rs, 'rt");
1659  break;
1660  case NOR:
1661  Format(instr, "nor 'rd, 'rs, 'rt");
1662  break;
1663  case SLT:
1664  Format(instr, "slt 'rd, 'rs, 'rt");
1665  break;
1666  case SLTU:
1667  Format(instr, "sltu 'rd, 'rs, 'rt");
1668  break;
1669  case TGE:
1670  Format(instr, "tge 'rs, 'rt, code: 'code");
1671  break;
1672  case TGEU:
1673  Format(instr, "tgeu 'rs, 'rt, code: 'code");
1674  break;
1675  case TLT:
1676  Format(instr, "tlt 'rs, 'rt, code: 'code");
1677  break;
1678  case TLTU:
1679  Format(instr, "tltu 'rs, 'rt, code: 'code");
1680  break;
1681  case TEQ:
1682  Format(instr, "teq 'rs, 'rt, code: 'code");
1683  break;
1684  case TNE:
1685  Format(instr, "tne 'rs, 'rt, code: 'code");
1686  break;
1687  case SYNC:
1688  Format(instr, "sync");
1689  break;
1690  case MOVZ:
1691  Format(instr, "movz 'rd, 'rs, 'rt");
1692  break;
1693  case MOVN:
1694  Format(instr, "movn 'rd, 'rs, 'rt");
1695  break;
1696  case MOVCI:
1697  if (instr->Bit(16)) {
1698  Format(instr, "movt 'rd, 'rs, 'bc");
1699  } else {
1700  Format(instr, "movf 'rd, 'rs, 'bc");
1701  }
1702  break;
1703  case SELEQZ_S:
1704  Format(instr, "seleqz 'rd, 'rs, 'rt");
1705  break;
1706  case SELNEZ_S:
1707  Format(instr, "selnez 'rd, 'rs, 'rt");
1708  break;
1709  default:
1710  UNREACHABLE();
1711  }
1712 }
1713 
1714 
1715 void Decoder::DecodeTypeRegisterSPECIAL2(Instruction* instr) {
1716  switch (instr->FunctionFieldRaw()) {
1717  case MUL:
1718  Format(instr, "mul 'rd, 'rs, 'rt");
1719  break;
1720  case CLZ:
1721  if (kArchVariant != kMips64r6) {
1722  Format(instr, "clz 'rd, 'rs");
1723  }
1724  break;
1725  case DCLZ:
1726  if (kArchVariant != kMips64r6) {
1727  Format(instr, "dclz 'rd, 'rs");
1728  }
1729  break;
1730  default:
1731  UNREACHABLE();
1732  }
1733 }
1734 
1735 
1736 void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) {
1737  switch (instr->FunctionFieldRaw()) {
1738  case EXT: {
1739  Format(instr, "ext 'rt, 'rs, 'sa, 'ss1");
1740  break;
1741  }
1742  case DEXT: {
1743  Format(instr, "dext 'rt, 'rs, 'sa, 'ss1");
1744  break;
1745  }
1746  case DEXTM: {
1747  Format(instr, "dextm 'rt, 'rs, 'sa, 'ss3");
1748  break;
1749  }
1750  case DEXTU: {
1751  Format(instr, "dextu 'rt, 'rs, 'ss5, 'ss1");
1752  break;
1753  }
1754  case INS: {
1755  Format(instr, "ins 'rt, 'rs, 'sa, 'ss2");
1756  break;
1757  }
1758  case DINS: {
1759  Format(instr, "dins 'rt, 'rs, 'sa, 'ss2");
1760  break;
1761  }
1762  case DINSM: {
1763  Format(instr, "dinsm 'rt, 'rs, 'sa, 'ss4");
1764  break;
1765  }
1766  case DINSU: {
1767  Format(instr, "dinsu 'rt, 'rs, 'ss5, 'ss2");
1768  break;
1769  }
1770  case BSHFL: {
1771  int sa = instr->SaFieldRaw() >> kSaShift;
1772  switch (sa) {
1773  case BITSWAP: {
1774  Format(instr, "bitswap 'rd, 'rt");
1775  break;
1776  }
1777  case SEB: {
1778  Format(instr, "seb 'rd, 'rt");
1779  break;
1780  }
1781  case SEH: {
1782  Format(instr, "seh 'rd, 'rt");
1783  break;
1784  }
1785  case WSBH: {
1786  Format(instr, "wsbh 'rd, 'rt");
1787  break;
1788  }
1789  default: {
1790  sa >>= kBp2Bits;
1791  switch (sa) {
1792  case ALIGN: {
1793  Format(instr, "align 'rd, 'rs, 'rt, 'bp2");
1794  break;
1795  }
1796  default:
1797  UNREACHABLE();
1798  break;
1799  }
1800  break;
1801  }
1802  }
1803  break;
1804  }
1805  case DBSHFL: {
1806  int sa = instr->SaFieldRaw() >> kSaShift;
1807  switch (sa) {
1808  case DBITSWAP: {
1809  switch (instr->SaFieldRaw() >> kSaShift) {
1810  case DBITSWAP_SA:
1811  Format(instr, "dbitswap 'rd, 'rt");
1812  break;
1813  default:
1814  UNREACHABLE();
1815  break;
1816  }
1817  break;
1818  }
1819  case DSBH: {
1820  Format(instr, "dsbh 'rd, 'rt");
1821  break;
1822  }
1823  case DSHD: {
1824  Format(instr, "dshd 'rd, 'rt");
1825  break;
1826  }
1827  default: {
1828  sa >>= kBp3Bits;
1829  switch (sa) {
1830  case DALIGN: {
1831  Format(instr, "dalign 'rd, 'rs, 'rt, 'bp3");
1832  break;
1833  }
1834  default:
1835  UNREACHABLE();
1836  break;
1837  }
1838  break;
1839  }
1840  }
1841  break;
1842  }
1843  default:
1844  UNREACHABLE();
1845  }
1846 }
1847 
1848 
1849 int Decoder::DecodeTypeRegister(Instruction* instr) {
1850  switch (instr->OpcodeFieldRaw()) {
1851  case COP1: // Coprocessor instructions.
1852  DecodeTypeRegisterCOP1(instr);
1853  break;
1854  case COP1X:
1855  DecodeTypeRegisterCOP1X(instr);
1856  break;
1857  case SPECIAL:
1858  switch (instr->FunctionFieldRaw()) {
1859  case BREAK:
1860  return DecodeBreakInstr(instr);
1861  default:
1862  DecodeTypeRegisterSPECIAL(instr);
1863  break;
1864  }
1865  break;
1866  case SPECIAL2:
1867  DecodeTypeRegisterSPECIAL2(instr);
1868  break;
1869  case SPECIAL3:
1870  DecodeTypeRegisterSPECIAL3(instr);
1871  break;
1872  case MSA:
1873  switch (instr->MSAMinorOpcodeField()) {
1874  case kMsaMinor3R:
1875  DecodeTypeMsa3R(instr);
1876  break;
1877  case kMsaMinor3RF:
1878  DecodeTypeMsa3RF(instr);
1879  break;
1880  case kMsaMinorVEC:
1881  DecodeTypeMsaVec(instr);
1882  break;
1883  case kMsaMinor2R:
1884  DecodeTypeMsa2R(instr);
1885  break;
1886  case kMsaMinor2RF:
1887  DecodeTypeMsa2RF(instr);
1888  break;
1889  case kMsaMinorELM:
1890  DecodeTypeMsaELM(instr);
1891  break;
1892  default:
1893  UNREACHABLE();
1894  }
1895  break;
1896  default:
1897  UNREACHABLE();
1898  }
1899  return kInstrSize;
1900 }
1901 
1902 void Decoder::DecodeTypeImmediateCOP1(Instruction* instr) {
1903  switch (instr->RsFieldRaw()) {
1904  case BC1:
1905  if (instr->FBtrueValue()) {
1906  Format(instr, "bc1t 'bc, 'imm16u -> 'imm16p4s2");
1907  } else {
1908  Format(instr, "bc1f 'bc, 'imm16u -> 'imm16p4s2");
1909  }
1910  break;
1911  case BC1EQZ:
1912  Format(instr, "bc1eqz 'ft, 'imm16u -> 'imm16p4s2");
1913  break;
1914  case BC1NEZ:
1915  Format(instr, "bc1nez 'ft, 'imm16u -> 'imm16p4s2");
1916  break;
1917  case BZ_V:
1918  case BZ_B:
1919  case BZ_H:
1920  case BZ_W:
1921  case BZ_D:
1922  Format(instr, "bz.'t 'wt, 'imm16s -> 'imm16p4s2");
1923  break;
1924  case BNZ_V:
1925  case BNZ_B:
1926  case BNZ_H:
1927  case BNZ_W:
1928  case BNZ_D:
1929  Format(instr, "bnz.'t 'wt, 'imm16s -> 'imm16p4s2");
1930  break;
1931  default:
1932  UNREACHABLE();
1933  }
1934 }
1935 
1936 
1937 void Decoder::DecodeTypeImmediateREGIMM(Instruction* instr) {
1938  switch (instr->RtFieldRaw()) {
1939  case BLTZ:
1940  Format(instr, "bltz 'rs, 'imm16u -> 'imm16p4s2");
1941  break;
1942  case BLTZAL:
1943  Format(instr, "bltzal 'rs, 'imm16u -> 'imm16p4s2");
1944  break;
1945  case BGEZ:
1946  Format(instr, "bgez 'rs, 'imm16u -> 'imm16p4s2");
1947  break;
1948  case BGEZAL: {
1949  if (instr->RsValue() == 0)
1950  Format(instr, "bal 'imm16s -> 'imm16p4s2");
1951  else
1952  Format(instr, "bgezal 'rs, 'imm16u -> 'imm16p4s2");
1953  break;
1954  }
1955  case BGEZALL:
1956  Format(instr, "bgezall 'rs, 'imm16u -> 'imm16p4s2");
1957  break;
1958  case DAHI:
1959  Format(instr, "dahi 'rs, 'imm16x");
1960  break;
1961  case DATI:
1962  Format(instr, "dati 'rs, 'imm16x");
1963  break;
1964  default:
1965  UNREACHABLE();
1966  }
1967 }
1968 
1969 void Decoder::DecodeTypeImmediateSPECIAL3(Instruction* instr) {
1970  switch (instr->FunctionFieldRaw()) {
1971  case LL_R6: {
1972  if (kArchVariant == kMips64r6) {
1973  Format(instr, "ll 'rt, 'imm9s('rs)");
1974  } else {
1975  Unknown(instr);
1976  }
1977  break;
1978  }
1979  case LLD_R6: {
1980  if (kArchVariant == kMips64r6) {
1981  Format(instr, "lld 'rt, 'imm9s('rs)");
1982  } else {
1983  Unknown(instr);
1984  }
1985  break;
1986  }
1987  case SC_R6: {
1988  if (kArchVariant == kMips64r6) {
1989  Format(instr, "sc 'rt, 'imm9s('rs)");
1990  } else {
1991  Unknown(instr);
1992  }
1993  break;
1994  }
1995  case SCD_R6: {
1996  if (kArchVariant == kMips64r6) {
1997  Format(instr, "scd 'rt, 'imm9s('rs)");
1998  } else {
1999  Unknown(instr);
2000  }
2001  break;
2002  }
2003  default:
2004  UNREACHABLE();
2005  }
2006 }
2007 
2008 void Decoder::DecodeTypeImmediate(Instruction* instr) {
2009  switch (instr->OpcodeFieldRaw()) {
2010  case COP1:
2011  DecodeTypeImmediateCOP1(instr);
2012  break; // Case COP1.
2013  // ------------- REGIMM class.
2014  case REGIMM:
2015  DecodeTypeImmediateREGIMM(instr);
2016  break; // Case REGIMM.
2017  // ------------- Branch instructions.
2018  case BEQ:
2019  Format(instr, "beq 'rs, 'rt, 'imm16u -> 'imm16p4s2");
2020  break;
2021  case BC:
2022  Format(instr, "bc 'imm26s -> 'imm26p4s2");
2023  break;
2024  case BALC:
2025  Format(instr, "balc 'imm26s -> 'imm26p4s2");
2026  break;
2027  case BNE:
2028  Format(instr, "bne 'rs, 'rt, 'imm16u -> 'imm16p4s2");
2029  break;
2030  case BLEZ:
2031  if ((instr->RtValue() == 0) && (instr->RsValue() != 0)) {
2032  Format(instr, "blez 'rs, 'imm16u -> 'imm16p4s2");
2033  } else if ((instr->RtValue() != instr->RsValue()) &&
2034  (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
2035  Format(instr, "bgeuc 'rs, 'rt, 'imm16u -> 'imm16p4s2");
2036  } else if ((instr->RtValue() == instr->RsValue()) &&
2037  (instr->RtValue() != 0)) {
2038  Format(instr, "bgezalc 'rs, 'imm16u -> 'imm16p4s2");
2039  } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
2040  Format(instr, "blezalc 'rt, 'imm16u -> 'imm16p4s2");
2041  } else {
2042  UNREACHABLE();
2043  }
2044  break;
2045  case BGTZ:
2046  if ((instr->RtValue() == 0) && (instr->RsValue() != 0)) {
2047  Format(instr, "bgtz 'rs, 'imm16u -> 'imm16p4s2");
2048  } else if ((instr->RtValue() != instr->RsValue()) &&
2049  (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
2050  Format(instr, "bltuc 'rs, 'rt, 'imm16u -> 'imm16p4s2");
2051  } else if ((instr->RtValue() == instr->RsValue()) &&
2052  (instr->RtValue() != 0)) {
2053  Format(instr, "bltzalc 'rt, 'imm16u -> 'imm16p4s2");
2054  } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
2055  Format(instr, "bgtzalc 'rt, 'imm16u -> 'imm16p4s2");
2056  } else {
2057  UNREACHABLE();
2058  }
2059  break;
2060  case BLEZL:
2061  if ((instr->RtValue() == instr->RsValue()) && (instr->RtValue() != 0)) {
2062  Format(instr, "bgezc 'rt, 'imm16u -> 'imm16p4s2");
2063  } else if ((instr->RtValue() != instr->RsValue()) &&
2064  (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
2065  Format(instr, "bgec 'rs, 'rt, 'imm16u -> 'imm16p4s2");
2066  } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
2067  Format(instr, "blezc 'rt, 'imm16u -> 'imm16p4s2");
2068  } else {
2069  UNREACHABLE();
2070  }
2071  break;
2072  case BGTZL:
2073  if ((instr->RtValue() == instr->RsValue()) && (instr->RtValue() != 0)) {
2074  Format(instr, "bltzc 'rt, 'imm16u -> 'imm16p4s2");
2075  } else if ((instr->RtValue() != instr->RsValue()) &&
2076  (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
2077  Format(instr, "bltc 'rs, 'rt, 'imm16u -> 'imm16p4s2");
2078  } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
2079  Format(instr, "bgtzc 'rt, 'imm16u -> 'imm16p4s2");
2080  } else {
2081  UNREACHABLE();
2082  }
2083  break;
2084  case POP66:
2085  if (instr->RsValue() == JIC) {
2086  Format(instr, "jic 'rt, 'imm16s");
2087  } else {
2088  Format(instr, "beqzc 'rs, 'imm21s -> 'imm21p4s2");
2089  }
2090  break;
2091  case POP76:
2092  if (instr->RsValue() == JIALC) {
2093  Format(instr, "jialc 'rt, 'imm16s");
2094  } else {
2095  Format(instr, "bnezc 'rs, 'imm21s -> 'imm21p4s2");
2096  }
2097  break;
2098  // ------------- Arithmetic instructions.
2099  case ADDI:
2100  if (kArchVariant != kMips64r6) {
2101  Format(instr, "addi 'rt, 'rs, 'imm16s");
2102  } else {
2103  int rs_reg = instr->RsValue();
2104  int rt_reg = instr->RtValue();
2105  // Check if BOVC, BEQZALC or BEQC instruction.
2106  if (rs_reg >= rt_reg) {
2107  Format(instr, "bovc 'rs, 'rt, 'imm16s -> 'imm16p4s2");
2108  } else {
2109  DCHECK_GT(rt_reg, 0);
2110  if (rs_reg == 0) {
2111  Format(instr, "beqzalc 'rt, 'imm16s -> 'imm16p4s2");
2112  } else {
2113  Format(instr, "beqc 'rs, 'rt, 'imm16s -> 'imm16p4s2");
2114  }
2115  }
2116  }
2117  break;
2118  case DADDI:
2119  if (kArchVariant != kMips64r6) {
2120  Format(instr, "daddi 'rt, 'rs, 'imm16s");
2121  } else {
2122  int rs_reg = instr->RsValue();
2123  int rt_reg = instr->RtValue();
2124  // Check if BNVC, BNEZALC or BNEC instruction.
2125  if (rs_reg >= rt_reg) {
2126  Format(instr, "bnvc 'rs, 'rt, 'imm16s -> 'imm16p4s2");
2127  } else {
2128  DCHECK_GT(rt_reg, 0);
2129  if (rs_reg == 0) {
2130  Format(instr, "bnezalc 'rt, 'imm16s -> 'imm16p4s2");
2131  } else {
2132  Format(instr, "bnec 'rs, 'rt, 'imm16s -> 'imm16p4s2");
2133  }
2134  }
2135  }
2136  break;
2137  case ADDIU:
2138  Format(instr, "addiu 'rt, 'rs, 'imm16s");
2139  break;
2140  case DADDIU:
2141  Format(instr, "daddiu 'rt, 'rs, 'imm16s");
2142  break;
2143  case SLTI:
2144  Format(instr, "slti 'rt, 'rs, 'imm16s");
2145  break;
2146  case SLTIU:
2147  Format(instr, "sltiu 'rt, 'rs, 'imm16u");
2148  break;
2149  case ANDI:
2150  Format(instr, "andi 'rt, 'rs, 'imm16x");
2151  break;
2152  case ORI:
2153  Format(instr, "ori 'rt, 'rs, 'imm16x");
2154  break;
2155  case XORI:
2156  Format(instr, "xori 'rt, 'rs, 'imm16x");
2157  break;
2158  case LUI:
2159  if (kArchVariant != kMips64r6) {
2160  Format(instr, "lui 'rt, 'imm16x");
2161  } else {
2162  if (instr->RsValue() != 0) {
2163  Format(instr, "aui 'rt, 'rs, 'imm16x");
2164  } else {
2165  Format(instr, "lui 'rt, 'imm16x");
2166  }
2167  }
2168  break;
2169  case DAUI:
2170  Format(instr, "daui 'rt, 'rs, 'imm16x");
2171  break;
2172  // ------------- Memory instructions.
2173  case LB:
2174  Format(instr, "lb 'rt, 'imm16s('rs)");
2175  break;
2176  case LH:
2177  Format(instr, "lh 'rt, 'imm16s('rs)");
2178  break;
2179  case LWL:
2180  Format(instr, "lwl 'rt, 'imm16s('rs)");
2181  break;
2182  case LDL:
2183  Format(instr, "ldl 'rt, 'imm16s('rs)");
2184  break;
2185  case LW:
2186  Format(instr, "lw 'rt, 'imm16s('rs)");
2187  break;
2188  case LWU:
2189  Format(instr, "lwu 'rt, 'imm16s('rs)");
2190  break;
2191  case LD:
2192  Format(instr, "ld 'rt, 'imm16s('rs)");
2193  break;
2194  case LBU:
2195  Format(instr, "lbu 'rt, 'imm16s('rs)");
2196  break;
2197  case LHU:
2198  Format(instr, "lhu 'rt, 'imm16s('rs)");
2199  break;
2200  case LWR:
2201  Format(instr, "lwr 'rt, 'imm16s('rs)");
2202  break;
2203  case LDR:
2204  Format(instr, "ldr 'rt, 'imm16s('rs)");
2205  break;
2206  case PREF:
2207  Format(instr, "pref 'rt, 'imm16s('rs)");
2208  break;
2209  case SB:
2210  Format(instr, "sb 'rt, 'imm16s('rs)");
2211  break;
2212  case SH:
2213  Format(instr, "sh 'rt, 'imm16s('rs)");
2214  break;
2215  case SWL:
2216  Format(instr, "swl 'rt, 'imm16s('rs)");
2217  break;
2218  case SW:
2219  Format(instr, "sw 'rt, 'imm16s('rs)");
2220  break;
2221  case SD:
2222  Format(instr, "sd 'rt, 'imm16s('rs)");
2223  break;
2224  case SWR:
2225  Format(instr, "swr 'rt, 'imm16s('rs)");
2226  break;
2227  case SDR:
2228  Format(instr, "sdr 'rt, 'imm16s('rs)");
2229  break;
2230  case SDL:
2231  Format(instr, "sdl 'rt, 'imm16s('rs)");
2232  break;
2233  case LL:
2234  if (kArchVariant == kMips64r6) {
2235  Unknown(instr);
2236  } else {
2237  Format(instr, "ll 'rt, 'imm16s('rs)");
2238  }
2239  break;
2240  case LLD:
2241  if (kArchVariant == kMips64r6) {
2242  Unknown(instr);
2243  } else {
2244  Format(instr, "lld 'rt, 'imm16s('rs)");
2245  }
2246  break;
2247  case SC:
2248  if (kArchVariant == kMips64r6) {
2249  Unknown(instr);
2250  } else {
2251  Format(instr, "sc 'rt, 'imm16s('rs)");
2252  }
2253  break;
2254  case SCD:
2255  if (kArchVariant == kMips64r6) {
2256  Unknown(instr);
2257  } else {
2258  Format(instr, "scd 'rt, 'imm16s('rs)");
2259  }
2260  break;
2261  case LWC1:
2262  Format(instr, "lwc1 'ft, 'imm16s('rs)");
2263  break;
2264  case LDC1:
2265  Format(instr, "ldc1 'ft, 'imm16s('rs)");
2266  break;
2267  case SWC1:
2268  Format(instr, "swc1 'ft, 'imm16s('rs)");
2269  break;
2270  case SDC1:
2271  Format(instr, "sdc1 'ft, 'imm16s('rs)");
2272  break;
2273  case PCREL: {
2274  int32_t imm21 = instr->Imm21Value();
2275  // rt field: 5-bits checking
2276  uint8_t rt = (imm21 >> kImm16Bits);
2277  switch (rt) {
2278  case ALUIPC:
2279  Format(instr, "aluipc 'rs, 'imm16s");
2280  break;
2281  case AUIPC:
2282  Format(instr, "auipc 'rs, 'imm16s");
2283  break;
2284  default: {
2285  // rt field: checking of the most significant 3-bits
2286  rt = (imm21 >> kImm18Bits);
2287  switch (rt) {
2288  case LDPC:
2289  Format(instr, "ldpc 'rs, 'imm18s");
2290  break;
2291  default: {
2292  // rt field: checking of the most significant 2-bits
2293  rt = (imm21 >> kImm19Bits);
2294  switch (rt) {
2295  case LWUPC:
2296  Format(instr, "lwupc 'rs, 'imm19s");
2297  break;
2298  case LWPC:
2299  Format(instr, "lwpc 'rs, 'imm19s");
2300  break;
2301  case ADDIUPC:
2302  Format(instr, "addiupc 'rs, 'imm19s");
2303  break;
2304  default:
2305  UNREACHABLE();
2306  break;
2307  }
2308  break;
2309  }
2310  }
2311  break;
2312  }
2313  }
2314  break;
2315  }
2316  case SPECIAL3:
2317  DecodeTypeImmediateSPECIAL3(instr);
2318  break;
2319  case MSA:
2320  switch (instr->MSAMinorOpcodeField()) {
2321  case kMsaMinorI8:
2322  DecodeTypeMsaI8(instr);
2323  break;
2324  case kMsaMinorI5:
2325  DecodeTypeMsaI5(instr);
2326  break;
2327  case kMsaMinorI10:
2328  DecodeTypeMsaI10(instr);
2329  break;
2330  case kMsaMinorELM:
2331  DecodeTypeMsaELM(instr);
2332  break;
2333  case kMsaMinorBIT:
2334  DecodeTypeMsaBIT(instr);
2335  break;
2336  case kMsaMinorMI10:
2337  DecodeTypeMsaMI10(instr);
2338  break;
2339  default:
2340  UNREACHABLE();
2341  break;
2342  }
2343  break;
2344  default:
2345  printf("a 0x%x \n", instr->OpcodeFieldRaw());
2346  UNREACHABLE();
2347  break;
2348  }
2349 }
2350 
2351 
2352 void Decoder::DecodeTypeJump(Instruction* instr) {
2353  switch (instr->OpcodeFieldRaw()) {
2354  case J:
2355  Format(instr, "j 'imm26x -> 'imm26j");
2356  break;
2357  case JAL:
2358  Format(instr, "jal 'imm26x -> 'imm26j");
2359  break;
2360  default:
2361  UNREACHABLE();
2362  }
2363 }
2364 
2365 void Decoder::DecodeTypeMsaI8(Instruction* instr) {
2366  uint32_t opcode = instr->InstructionBits() & kMsaI8Mask;
2367 
2368  switch (opcode) {
2369  case ANDI_B:
2370  Format(instr, "andi.b 'wd, 'ws, 'imm8");
2371  break;
2372  case ORI_B:
2373  Format(instr, "ori.b 'wd, 'ws, 'imm8");
2374  break;
2375  case NORI_B:
2376  Format(instr, "nori.b 'wd, 'ws, 'imm8");
2377  break;
2378  case XORI_B:
2379  Format(instr, "xori.b 'wd, 'ws, 'imm8");
2380  break;
2381  case BMNZI_B:
2382  Format(instr, "bmnzi.b 'wd, 'ws, 'imm8");
2383  break;
2384  case BMZI_B:
2385  Format(instr, "bmzi.b 'wd, 'ws, 'imm8");
2386  break;
2387  case BSELI_B:
2388  Format(instr, "bseli.b 'wd, 'ws, 'imm8");
2389  break;
2390  case SHF_B:
2391  Format(instr, "shf.b 'wd, 'ws, 'imm8");
2392  break;
2393  case SHF_H:
2394  Format(instr, "shf.h 'wd, 'ws, 'imm8");
2395  break;
2396  case SHF_W:
2397  Format(instr, "shf.w 'wd, 'ws, 'imm8");
2398  break;
2399  default:
2400  UNREACHABLE();
2401  }
2402 }
2403 
2404 void Decoder::DecodeTypeMsaI5(Instruction* instr) {
2405  uint32_t opcode = instr->InstructionBits() & kMsaI5Mask;
2406 
2407  switch (opcode) {
2408  case ADDVI:
2409  Format(instr, "addvi.'t 'wd, 'ws, 'imm5u");
2410  break;
2411  case SUBVI:
2412  Format(instr, "subvi.'t 'wd, 'ws, 'imm5u");
2413  break;
2414  case MAXI_S:
2415  Format(instr, "maxi_s.'t 'wd, 'ws, 'imm5s");
2416  break;
2417  case MAXI_U:
2418  Format(instr, "maxi_u.'t 'wd, 'ws, 'imm5u");
2419  break;
2420  case MINI_S:
2421  Format(instr, "mini_s.'t 'wd, 'ws, 'imm5s");
2422  break;
2423  case MINI_U:
2424  Format(instr, "mini_u.'t 'wd, 'ws, 'imm5u");
2425  break;
2426  case CEQI:
2427  Format(instr, "ceqi.'t 'wd, 'ws, 'imm5s");
2428  break;
2429  case CLTI_S:
2430  Format(instr, "clti_s.'t 'wd, 'ws, 'imm5s");
2431  break;
2432  case CLTI_U:
2433  Format(instr, "clti_u.'t 'wd, 'ws, 'imm5u");
2434  break;
2435  case CLEI_S:
2436  Format(instr, "clei_s.'t 'wd, 'ws, 'imm5s");
2437  break;
2438  case CLEI_U:
2439  Format(instr, "clei_u.'t 'wd, 'ws, 'imm5u");
2440  break;
2441  default:
2442  UNREACHABLE();
2443  }
2444 }
2445 
2446 void Decoder::DecodeTypeMsaI10(Instruction* instr) {
2447  uint32_t opcode = instr->InstructionBits() & kMsaI5Mask;
2448  if (opcode == LDI) {
2449  Format(instr, "ldi.'t 'wd, 'imm10s1");
2450  } else {
2451  UNREACHABLE();
2452  }
2453 }
2454 
2455 void Decoder::DecodeTypeMsaELM(Instruction* instr) {
2456  uint32_t opcode = instr->InstructionBits() & kMsaELMMask;
2457  switch (opcode) {
2458  case SLDI:
2459  if (instr->Bits(21, 16) == 0x3E) {
2460  Format(instr, "ctcmsa ");
2461  PrintMSAControlRegister(instr->WdValue());
2462  Print(", ");
2463  PrintRegister(instr->WsValue());
2464  } else {
2465  Format(instr, "sldi.'t 'wd, 'ws['imme]");
2466  }
2467  break;
2468  case SPLATI:
2469  if (instr->Bits(21, 16) == 0x3E) {
2470  Format(instr, "cfcmsa ");
2471  PrintRegister(instr->WdValue());
2472  Print(", ");
2473  PrintMSAControlRegister(instr->WsValue());
2474  } else {
2475  Format(instr, "splati.'t 'wd, 'ws['imme]");
2476  }
2477  break;
2478  case COPY_S:
2479  if (instr->Bits(21, 16) == 0x3E) {
2480  Format(instr, "move.v 'wd, 'ws");
2481  } else {
2482  Format(instr, "copy_s.'t ");
2483  PrintMsaCopy(instr);
2484  }
2485  break;
2486  case COPY_U:
2487  Format(instr, "copy_u.'t ");
2488  PrintMsaCopy(instr);
2489  break;
2490  case INSERT:
2491  Format(instr, "insert.'t 'wd['imme], ");
2492  PrintRegister(instr->WsValue());
2493  break;
2494  case INSVE:
2495  Format(instr, "insve.'t 'wd['imme], 'ws[0]");
2496  break;
2497  default:
2498  UNREACHABLE();
2499  }
2500 }
2501 
2502 void Decoder::DecodeTypeMsaBIT(Instruction* instr) {
2503  uint32_t opcode = instr->InstructionBits() & kMsaBITMask;
2504 
2505  switch (opcode) {
2506  case SLLI:
2507  Format(instr, "slli.'t 'wd, 'ws, 'immb");
2508  break;
2509  case SRAI:
2510  Format(instr, "srai.'t 'wd, 'ws, 'immb");
2511  break;
2512  case SRLI:
2513  Format(instr, "srli.'t 'wd, 'ws, 'immb");
2514  break;
2515  case BCLRI:
2516  Format(instr, "bclri.'t 'wd, 'ws, 'immb");
2517  break;
2518  case BSETI:
2519  Format(instr, "bseti.'t 'wd, 'ws, 'immb");
2520  break;
2521  case BNEGI:
2522  Format(instr, "bnegi.'t 'wd, 'ws, 'immb");
2523  break;
2524  case BINSLI:
2525  Format(instr, "binsli.'t 'wd, 'ws, 'immb");
2526  break;
2527  case BINSRI:
2528  Format(instr, "binsri.'t 'wd, 'ws, 'immb");
2529  break;
2530  case SAT_S:
2531  Format(instr, "sat_s.'t 'wd, 'ws, 'immb");
2532  break;
2533  case SAT_U:
2534  Format(instr, "sat_u.'t 'wd, 'ws, 'immb");
2535  break;
2536  case SRARI:
2537  Format(instr, "srari.'t 'wd, 'ws, 'immb");
2538  break;
2539  case SRLRI:
2540  Format(instr, "srlri.'t 'wd, 'ws, 'immb");
2541  break;
2542  default:
2543  UNREACHABLE();
2544  }
2545 }
2546 
2547 void Decoder::DecodeTypeMsaMI10(Instruction* instr) {
2548  uint32_t opcode = instr->InstructionBits() & kMsaMI10Mask;
2549  if (opcode == MSA_LD) {
2550  Format(instr, "ld.'t 'wd, 'imm10s2(");
2551  PrintRegister(instr->WsValue());
2552  Print(")");
2553  } else if (opcode == MSA_ST) {
2554  Format(instr, "st.'t 'wd, 'imm10s2(");
2555  PrintRegister(instr->WsValue());
2556  Print(")");
2557  } else {
2558  UNREACHABLE();
2559  }
2560 }
2561 
2562 void Decoder::DecodeTypeMsa3R(Instruction* instr) {
2563  uint32_t opcode = instr->InstructionBits() & kMsa3RMask;
2564  switch (opcode) {
2565  case SLL_MSA:
2566  Format(instr, "sll.'t 'wd, 'ws, 'wt");
2567  break;
2568  case SRA_MSA:
2569  Format(instr, "sra.'t 'wd, 'ws, 'wt");
2570  break;
2571  case SRL_MSA:
2572  Format(instr, "srl.'t 'wd, 'ws, 'wt");
2573  break;
2574  case BCLR:
2575  Format(instr, "bclr.'t 'wd, 'ws, 'wt");
2576  break;
2577  case BSET:
2578  Format(instr, "bset.'t 'wd, 'ws, 'wt");
2579  break;
2580  case BNEG:
2581  Format(instr, "bneg.'t 'wd, 'ws, 'wt");
2582  break;
2583  case BINSL:
2584  Format(instr, "binsl.'t 'wd, 'ws, 'wt");
2585  break;
2586  case BINSR:
2587  Format(instr, "binsr.'t 'wd, 'ws, 'wt");
2588  break;
2589  case ADDV:
2590  Format(instr, "addv.'t 'wd, 'ws, 'wt");
2591  break;
2592  case SUBV:
2593  Format(instr, "subv.'t 'wd, 'ws, 'wt");
2594  break;
2595  case MAX_S:
2596  Format(instr, "max_s.'t 'wd, 'ws, 'wt");
2597  break;
2598  case MAX_U:
2599  Format(instr, "max_u.'t 'wd, 'ws, 'wt");
2600  break;
2601  case MIN_S:
2602  Format(instr, "min_s.'t 'wd, 'ws, 'wt");
2603  break;
2604  case MIN_U:
2605  Format(instr, "min_u.'t 'wd, 'ws, 'wt");
2606  break;
2607  case MAX_A:
2608  Format(instr, "max_a.'t 'wd, 'ws, 'wt");
2609  break;
2610  case MIN_A:
2611  Format(instr, "min_a.'t 'wd, 'ws, 'wt");
2612  break;
2613  case CEQ:
2614  Format(instr, "ceq.'t 'wd, 'ws, 'wt");
2615  break;
2616  case CLT_S:
2617  Format(instr, "clt_s.'t 'wd, 'ws, 'wt");
2618  break;
2619  case CLT_U:
2620  Format(instr, "clt_u.'t 'wd, 'ws, 'wt");
2621  break;
2622  case CLE_S:
2623  Format(instr, "cle_s.'t 'wd, 'ws, 'wt");
2624  break;
2625  case CLE_U:
2626  Format(instr, "cle_u.'t 'wd, 'ws, 'wt");
2627  break;
2628  case ADD_A:
2629  Format(instr, "add_a.'t 'wd, 'ws, 'wt");
2630  break;
2631  case ADDS_A:
2632  Format(instr, "adds_a.'t 'wd, 'ws, 'wt");
2633  break;
2634  case ADDS_S:
2635  Format(instr, "adds_s.'t 'wd, 'ws, 'wt");
2636  break;
2637  case ADDS_U:
2638  Format(instr, "adds_u.'t 'wd, 'ws, 'wt");
2639  break;
2640  case AVE_S:
2641  Format(instr, "ave_s.'t 'wd, 'ws, 'wt");
2642  break;
2643  case AVE_U:
2644  Format(instr, "ave_u.'t 'wd, 'ws, 'wt");
2645  break;
2646  case AVER_S:
2647  Format(instr, "aver_s.'t 'wd, 'ws, 'wt");
2648  break;
2649  case AVER_U:
2650  Format(instr, "aver_u.'t 'wd, 'ws, 'wt");
2651  break;
2652  case SUBS_S:
2653  Format(instr, "subs_s.'t 'wd, 'ws, 'wt");
2654  break;
2655  case SUBS_U:
2656  Format(instr, "subs_u.'t 'wd, 'ws, 'wt");
2657  break;
2658  case SUBSUS_U:
2659  Format(instr, "subsus_u.'t 'wd, 'ws, 'wt");
2660  break;
2661  case SUBSUU_S:
2662  Format(instr, "subsuu_s.'t 'wd, 'ws, 'wt");
2663  break;
2664  case ASUB_S:
2665  Format(instr, "asub_s.'t 'wd, 'ws, 'wt");
2666  break;
2667  case ASUB_U:
2668  Format(instr, "asub_u.'t 'wd, 'ws, 'wt");
2669  break;
2670  case MULV:
2671  Format(instr, "mulv.'t 'wd, 'ws, 'wt");
2672  break;
2673  case MADDV:
2674  Format(instr, "maddv.'t 'wd, 'ws, 'wt");
2675  break;
2676  case MSUBV:
2677  Format(instr, "msubv.'t 'wd, 'ws, 'wt");
2678  break;
2679  case DIV_S_MSA:
2680  Format(instr, "div_s.'t 'wd, 'ws, 'wt");
2681  break;
2682  case DIV_U:
2683  Format(instr, "div_u.'t 'wd, 'ws, 'wt");
2684  break;
2685  case MOD_S:
2686  Format(instr, "mod_s.'t 'wd, 'ws, 'wt");
2687  break;
2688  case MOD_U:
2689  Format(instr, "mod_u.'t 'wd, 'ws, 'wt");
2690  break;
2691  case DOTP_S:
2692  Format(instr, "dotp_s.'t 'wd, 'ws, 'wt");
2693  break;
2694  case DOTP_U:
2695  Format(instr, "dotp_u.'t 'wd, 'ws, 'wt");
2696  break;
2697  case DPADD_S:
2698  Format(instr, "dpadd_s.'t 'wd, 'ws, 'wt");
2699  break;
2700  case DPADD_U:
2701  Format(instr, "dpadd_u.'t 'wd, 'ws, 'wt");
2702  break;
2703  case DPSUB_S:
2704  Format(instr, "dpsub_s.'t 'wd, 'ws, 'wt");
2705  break;
2706  case DPSUB_U:
2707  Format(instr, "dpsub_u.'t 'wd, 'ws, 'wt");
2708  break;
2709  case SLD:
2710  Format(instr, "sld.'t 'wd, 'ws['rt]");
2711  break;
2712  case SPLAT:
2713  Format(instr, "splat.'t 'wd, 'ws['rt]");
2714  break;
2715  case PCKEV:
2716  Format(instr, "pckev.'t 'wd, 'ws, 'wt");
2717  break;
2718  case PCKOD:
2719  Format(instr, "pckod.'t 'wd, 'ws, 'wt");
2720  break;
2721  case ILVL:
2722  Format(instr, "ilvl.'t 'wd, 'ws, 'wt");
2723  break;
2724  case ILVR:
2725  Format(instr, "ilvr.'t 'wd, 'ws, 'wt");
2726  break;
2727  case ILVEV:
2728  Format(instr, "ilvev.'t 'wd, 'ws, 'wt");
2729  break;
2730  case ILVOD:
2731  Format(instr, "ilvod.'t 'wd, 'ws, 'wt");
2732  break;
2733  case VSHF:
2734  Format(instr, "vshf.'t 'wd, 'ws, 'wt");
2735  break;
2736  case SRAR:
2737  Format(instr, "srar.'t 'wd, 'ws, 'wt");
2738  break;
2739  case SRLR:
2740  Format(instr, "srlr.'t 'wd, 'ws, 'wt");
2741  break;
2742  case HADD_S:
2743  Format(instr, "hadd_s.'t 'wd, 'ws, 'wt");
2744  break;
2745  case HADD_U:
2746  Format(instr, "hadd_u.'t 'wd, 'ws, 'wt");
2747  break;
2748  case HSUB_S:
2749  Format(instr, "hsub_s.'t 'wd, 'ws, 'wt");
2750  break;
2751  case HSUB_U:
2752  Format(instr, "hsub_u.'t 'wd, 'ws, 'wt");
2753  break;
2754  default:
2755  UNREACHABLE();
2756  }
2757 }
2758 
2759 void Decoder::DecodeTypeMsa3RF(Instruction* instr) {
2760  uint32_t opcode = instr->InstructionBits() & kMsa3RFMask;
2761  switch (opcode) {
2762  case FCAF:
2763  Format(instr, "fcaf.'t 'wd, 'ws, 'wt");
2764  break;
2765  case FCUN:
2766  Format(instr, "fcun.'t 'wd, 'ws, 'wt");
2767  break;
2768  case FCEQ:
2769  Format(instr, "fceq.'t 'wd, 'ws, 'wt");
2770  break;
2771  case FCUEQ:
2772  Format(instr, "fcueq.'t 'wd, 'ws, 'wt");
2773  break;
2774  case FCLT:
2775  Format(instr, "fclt.'t 'wd, 'ws, 'wt");
2776  break;
2777  case FCULT:
2778  Format(instr, "fcult.'t 'wd, 'ws, 'wt");
2779  break;
2780  case FCLE:
2781  Format(instr, "fcle.'t 'wd, 'ws, 'wt");
2782  break;
2783  case FCULE:
2784  Format(instr, "fcule.'t 'wd, 'ws, 'wt");
2785  break;
2786  case FSAF:
2787  Format(instr, "fsaf.'t 'wd, 'ws, 'wt");
2788  break;
2789  case FSUN:
2790  Format(instr, "fsun.'t 'wd, 'ws, 'wt");
2791  break;
2792  case FSEQ:
2793  Format(instr, "fseq.'t 'wd, 'ws, 'wt");
2794  break;
2795  case FSUEQ:
2796  Format(instr, "fsueq.'t 'wd, 'ws, 'wt");
2797  break;
2798  case FSLT:
2799  Format(instr, "fslt.'t 'wd, 'ws, 'wt");
2800  break;
2801  case FSULT:
2802  Format(instr, "fsult.'t 'wd, 'ws, 'wt");
2803  break;
2804  case FSLE:
2805  Format(instr, "fsle.'t 'wd, 'ws, 'wt");
2806  break;
2807  case FSULE:
2808  Format(instr, "fsule.'t 'wd, 'ws, 'wt");
2809  break;
2810  case FADD:
2811  Format(instr, "fadd.'t 'wd, 'ws, 'wt");
2812  break;
2813  case FSUB:
2814  Format(instr, "fsub.'t 'wd, 'ws, 'wt");
2815  break;
2816  case FMUL:
2817  Format(instr, "fmul.'t 'wd, 'ws, 'wt");
2818  break;
2819  case FDIV:
2820  Format(instr, "fdiv.'t 'wd, 'ws, 'wt");
2821  break;
2822  case FMADD:
2823  Format(instr, "fmadd.'t 'wd, 'ws, 'wt");
2824  break;
2825  case FMSUB:
2826  Format(instr, "fmsub.'t 'wd, 'ws, 'wt");
2827  break;
2828  case FEXP2:
2829  Format(instr, "fexp2.'t 'wd, 'ws, 'wt");
2830  break;
2831  case FEXDO:
2832  Format(instr, "fexdo.'t 'wd, 'ws, 'wt");
2833  break;
2834  case FTQ:
2835  Format(instr, "ftq.'t 'wd, 'ws, 'wt");
2836  break;
2837  case FMIN:
2838  Format(instr, "fmin.'t 'wd, 'ws, 'wt");
2839  break;
2840  case FMIN_A:
2841  Format(instr, "fmin_a.'t 'wd, 'ws, 'wt");
2842  break;
2843  case FMAX:
2844  Format(instr, "fmax.'t 'wd, 'ws, 'wt");
2845  break;
2846  case FMAX_A:
2847  Format(instr, "fmax_a.'t 'wd, 'ws, 'wt");
2848  break;
2849  case FCOR:
2850  Format(instr, "fcor.'t 'wd, 'ws, 'wt");
2851  break;
2852  case FCUNE:
2853  Format(instr, "fcune.'t 'wd, 'ws, 'wt");
2854  break;
2855  case FCNE:
2856  Format(instr, "fcne.'t 'wd, 'ws, 'wt");
2857  break;
2858  case MUL_Q:
2859  Format(instr, "mul_q.'t 'wd, 'ws, 'wt");
2860  break;
2861  case MADD_Q:
2862  Format(instr, "madd_q.'t 'wd, 'ws, 'wt");
2863  break;
2864  case MSUB_Q:
2865  Format(instr, "msub_q.'t 'wd, 'ws, 'wt");
2866  break;
2867  case FSOR:
2868  Format(instr, "fsor.'t 'wd, 'ws, 'wt");
2869  break;
2870  case FSUNE:
2871  Format(instr, "fsune.'t 'wd, 'ws, 'wt");
2872  break;
2873  case FSNE:
2874  Format(instr, "fsne.'t 'wd, 'ws, 'wt");
2875  break;
2876  case MULR_Q:
2877  Format(instr, "mulr_q.'t 'wd, 'ws, 'wt");
2878  break;
2879  case MADDR_Q:
2880  Format(instr, "maddr_q.'t 'wd, 'ws, 'wt");
2881  break;
2882  case MSUBR_Q:
2883  Format(instr, "msubr_q.'t 'wd, 'ws, 'wt");
2884  break;
2885  default:
2886  UNREACHABLE();
2887  }
2888 }
2889 
2890 void Decoder::DecodeTypeMsaVec(Instruction* instr) {
2891  uint32_t opcode = instr->InstructionBits() & kMsaVECMask;
2892  switch (opcode) {
2893  case AND_V:
2894  Format(instr, "and.v 'wd, 'ws, 'wt");
2895  break;
2896  case OR_V:
2897  Format(instr, "or.v 'wd, 'ws, 'wt");
2898  break;
2899  case NOR_V:
2900  Format(instr, "nor.v 'wd, 'ws, 'wt");
2901  break;
2902  case XOR_V:
2903  Format(instr, "xor.v 'wd, 'ws, 'wt");
2904  break;
2905  case BMNZ_V:
2906  Format(instr, "bmnz.v 'wd, 'ws, 'wt");
2907  break;
2908  case BMZ_V:
2909  Format(instr, "bmz.v 'wd, 'ws, 'wt");
2910  break;
2911  case BSEL_V:
2912  Format(instr, "bsel.v 'wd, 'ws, 'wt");
2913  break;
2914  default:
2915  UNREACHABLE();
2916  }
2917 }
2918 
2919 void Decoder::DecodeTypeMsa2R(Instruction* instr) {
2920  uint32_t opcode = instr->InstructionBits() & kMsa2RMask;
2921  switch (opcode) {
2922  case FILL: {
2923  Format(instr, "fill.'t 'wd, ");
2924  PrintRegister(instr->WsValue()); // rs value is in ws field
2925  } break;
2926  case PCNT:
2927  Format(instr, "pcnt.'t 'wd, 'ws");
2928  break;
2929  case NLOC:
2930  Format(instr, "nloc.'t 'wd, 'ws");
2931  break;
2932  case NLZC:
2933  Format(instr, "nlzc.'t 'wd, 'ws");
2934  break;
2935  default:
2936  UNREACHABLE();
2937  }
2938 }
2939 
2940 void Decoder::DecodeTypeMsa2RF(Instruction* instr) {
2941  uint32_t opcode = instr->InstructionBits() & kMsa2RFMask;
2942  switch (opcode) {
2943  case FCLASS:
2944  Format(instr, "fclass.'t 'wd, 'ws");
2945  break;
2946  case FTRUNC_S:
2947  Format(instr, "ftrunc_s.'t 'wd, 'ws");
2948  break;
2949  case FTRUNC_U:
2950  Format(instr, "ftrunc_u.'t 'wd, 'ws");
2951  break;
2952  case FSQRT:
2953  Format(instr, "fsqrt.'t 'wd, 'ws");
2954  break;
2955  case FRSQRT:
2956  Format(instr, "frsqrt.'t 'wd, 'ws");
2957  break;
2958  case FRCP:
2959  Format(instr, "frcp.'t 'wd, 'ws");
2960  break;
2961  case FRINT:
2962  Format(instr, "frint.'t 'wd, 'ws");
2963  break;
2964  case FLOG2:
2965  Format(instr, "flog2.'t 'wd, 'ws");
2966  break;
2967  case FEXUPL:
2968  Format(instr, "fexupl.'t 'wd, 'ws");
2969  break;
2970  case FEXUPR:
2971  Format(instr, "fexupr.'t 'wd, 'ws");
2972  break;
2973  case FFQL:
2974  Format(instr, "ffql.'t 'wd, 'ws");
2975  break;
2976  case FFQR:
2977  Format(instr, "ffqr.'t 'wd, 'ws");
2978  break;
2979  case FTINT_S:
2980  Format(instr, "ftint_s.'t 'wd, 'ws");
2981  break;
2982  case FTINT_U:
2983  Format(instr, "ftint_u.'t 'wd, 'ws");
2984  break;
2985  case FFINT_S:
2986  Format(instr, "ffint_s.'t 'wd, 'ws");
2987  break;
2988  case FFINT_U:
2989  Format(instr, "ffint_u.'t 'wd, 'ws");
2990  break;
2991  default:
2992  UNREACHABLE();
2993  }
2994 }
2995 
2996 
2997 // Disassemble the instruction at *instr_ptr into the output buffer.
2998 // All instructions are one word long, except for the simulator
2999 // pseudo-instruction stop(msg). For that one special case, we return
3000 // size larger than one kInstrSize.
3001 int Decoder::InstructionDecode(byte* instr_ptr) {
3002  Instruction* instr = Instruction::At(instr_ptr);
3003  // Print raw instruction bytes.
3004  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
3005  "%08x ",
3006  instr->InstructionBits());
3007  switch (instr->InstructionType()) {
3008  case Instruction::kRegisterType: {
3009  return DecodeTypeRegister(instr);
3010  }
3011  case Instruction::kImmediateType: {
3012  DecodeTypeImmediate(instr);
3013  break;
3014  }
3015  case Instruction::kJumpType: {
3016  DecodeTypeJump(instr);
3017  break;
3018  }
3019  default: {
3020  Format(instr, "UNSUPPORTED");
3021  UNSUPPORTED_MIPS();
3022  }
3023  }
3024  return kInstrSize;
3025 }
3026 
3027 } // namespace internal
3028 } // namespace v8
3029 
3030 
3031 //------------------------------------------------------------------------------
3032 
3033 namespace disasm {
3034 
3035 const char* NameConverter::NameOfAddress(byte* addr) const {
3036  v8::internal::SNPrintF(tmp_buffer_, "%p", static_cast<void*>(addr));
3037  return tmp_buffer_.start();
3038 }
3039 
3040 
3041 const char* NameConverter::NameOfConstant(byte* addr) const {
3042  return NameOfAddress(addr);
3043 }
3044 
3045 
3046 const char* NameConverter::NameOfCPURegister(int reg) const {
3047  return v8::internal::Registers::Name(reg);
3048 }
3049 
3050 
3051 const char* NameConverter::NameOfXMMRegister(int reg) const {
3052  return v8::internal::FPURegisters::Name(reg);
3053 }
3054 
3055 
3056 const char* NameConverter::NameOfByteCPURegister(int reg) const {
3057  UNREACHABLE(); // MIPS does not have the concept of a byte register.
3058  return "nobytereg";
3059 }
3060 
3061 
3062 const char* NameConverter::NameInCode(byte* addr) const {
3063  // The default name converter is called for unknown code. So we will not try
3064  // to access any memory.
3065  return "";
3066 }
3067 
3068 
3069 //------------------------------------------------------------------------------
3070 
3071 int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
3072  byte* instruction) {
3073  v8::internal::Decoder d(converter_, buffer);
3074  return d.InstructionDecode(instruction);
3075 }
3076 
3077 
3078 // The MIPS assembler does not currently use constant pools.
3079 int Disassembler::ConstantPoolSizeAt(byte* instruction) {
3080  return -1;
3081 }
3082 
3083 void Disassembler::Disassemble(FILE* f, byte* begin, byte* end,
3084  UnimplementedOpcodeAction unimplemented_action) {
3085  NameConverter converter;
3086  Disassembler d(converter, unimplemented_action);
3087  for (byte* pc = begin; pc < end;) {
3088  v8::internal::EmbeddedVector<char, 128> buffer;
3089  buffer[0] = '\0';
3090  byte* prev_pc = pc;
3091  pc += d.InstructionDecode(buffer, pc);
3092  v8::internal::PrintF(f, "%p %08x %s\n", static_cast<void*>(prev_pc),
3093  *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
3094  }
3095 }
3096 
3097 
3098 #undef UNSUPPORTED
3099 
3100 } // namespace disasm
3101 
3102 #endif // V8_TARGET_ARCH_MIPS64
v8
Definition: libplatform.h:13
uint32_t
disasm
Definition: disasm.h:10