V8 API Reference, 7.2.502.16 (for Deno 0.2.4)
constants-arm64.h
1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_
6 #define V8_ARM64_CONSTANTS_ARM64_H_
7 
8 #include "src/base/macros.h"
9 #include "src/globals.h"
10 
11 // Assert that this is an LP64 system, or LLP64 on Windows.
12 STATIC_ASSERT(sizeof(int) == sizeof(int32_t));
13 #if defined(V8_OS_WIN)
14 STATIC_ASSERT(sizeof(1L) == sizeof(int32_t));
15 #else
16 STATIC_ASSERT(sizeof(long) == sizeof(int64_t)); // NOLINT(runtime/int)
17 STATIC_ASSERT(sizeof(1L) == sizeof(int64_t));
18 #endif
19 STATIC_ASSERT(sizeof(void *) == sizeof(int64_t));
20 STATIC_ASSERT(sizeof(1) == sizeof(int32_t));
21 
22 
23 // Get the standard printf format macros for C99 stdint types.
24 #ifndef __STDC_FORMAT_MACROS
25 #define __STDC_FORMAT_MACROS
26 #endif
27 #include <inttypes.h>
28 
29 
30 namespace v8 {
31 namespace internal {
32 
33 constexpr size_t kMaxPCRelativeCodeRangeInMB = 128;
34 
35 constexpr uint8_t kInstrSize = 4;
36 constexpr uint8_t kInstrSizeLog2 = 2;
37 constexpr size_t kLoadLiteralScaleLog2 = 2;
38 constexpr size_t kMaxLoadLiteralRange = 1 * MB;
39 
40 const int kNumberOfRegisters = 32;
41 const int kNumberOfVRegisters = 32;
42 // Callee saved registers are x19-x30(lr).
43 const int kNumberOfCalleeSavedRegisters = 11;
44 const int kFirstCalleeSavedRegisterIndex = 19;
45 // Callee saved FP registers are d8-d15.
46 const int kNumberOfCalleeSavedVRegisters = 8;
47 const int kFirstCalleeSavedVRegisterIndex = 8;
48 // Callee saved registers with no specific purpose in JS are x19-x25.
49 const size_t kJSCalleeSavedRegList = 0x03f80000;
50 const int kWRegSizeInBits = 32;
51 const int kWRegSizeInBitsLog2 = 5;
52 const int kWRegSize = kWRegSizeInBits >> 3;
53 const int kWRegSizeLog2 = kWRegSizeInBitsLog2 - 3;
54 const int kXRegSizeInBits = 64;
55 const int kXRegSizeInBitsLog2 = 6;
56 const int kXRegSize = kXRegSizeInBits >> 3;
57 const int kXRegSizeLog2 = kXRegSizeInBitsLog2 - 3;
58 const int kSRegSizeInBits = 32;
59 const int kSRegSizeInBitsLog2 = 5;
60 const int kSRegSize = kSRegSizeInBits >> 3;
61 const int kSRegSizeLog2 = kSRegSizeInBitsLog2 - 3;
62 const int kDRegSizeInBits = 64;
63 const int kDRegSizeInBitsLog2 = 6;
64 const int kDRegSize = kDRegSizeInBits >> 3;
65 const int kDRegSizeLog2 = kDRegSizeInBitsLog2 - 3;
66 const int kDRegSizeInBytesLog2 = kDRegSizeInBitsLog2 - 3;
67 const int kBRegSizeInBits = 8;
68 const int kBRegSize = kBRegSizeInBits >> 3;
69 const int kHRegSizeInBits = 16;
70 const int kHRegSize = kHRegSizeInBits >> 3;
71 const int kQRegSizeInBits = 128;
72 const int kQRegSizeInBitsLog2 = 7;
73 const int kQRegSize = kQRegSizeInBits >> 3;
74 const int kQRegSizeLog2 = kQRegSizeInBitsLog2 - 3;
75 const int kVRegSizeInBits = kQRegSizeInBits;
76 const int kVRegSize = kVRegSizeInBits >> 3;
77 const int64_t kWRegMask = 0x00000000ffffffffL;
78 const int64_t kXRegMask = 0xffffffffffffffffL;
79 const int64_t kSRegMask = 0x00000000ffffffffL;
80 const int64_t kDRegMask = 0xffffffffffffffffL;
81 // TODO(all) check if the expression below works on all compilers or if it
82 // triggers an overflow error.
83 const int64_t kDSignBit = 63;
84 const int64_t kDSignMask = 0x1LL << kDSignBit;
85 const int64_t kSSignBit = 31;
86 const int64_t kSSignMask = 0x1LL << kSSignBit;
87 const int64_t kXSignBit = 63;
88 const int64_t kXSignMask = 0x1LL << kXSignBit;
89 const int64_t kWSignBit = 31;
90 const int64_t kWSignMask = 0x1LL << kWSignBit;
91 const int64_t kDQuietNanBit = 51;
92 const int64_t kDQuietNanMask = 0x1LL << kDQuietNanBit;
93 const int64_t kSQuietNanBit = 22;
94 const int64_t kSQuietNanMask = 0x1LL << kSQuietNanBit;
95 const int64_t kByteMask = 0xffL;
96 const int64_t kHalfWordMask = 0xffffL;
97 const int64_t kWordMask = 0xffffffffL;
98 const uint64_t kXMaxUInt = 0xffffffffffffffffUL;
99 const uint64_t kWMaxUInt = 0xffffffffUL;
100 const int64_t kXMaxInt = 0x7fffffffffffffffL;
101 const int64_t kXMinInt = 0x8000000000000000L;
102 const int32_t kWMaxInt = 0x7fffffff;
103 const int32_t kWMinInt = 0x80000000;
104 const int kIp0Code = 16;
105 const int kIp1Code = 17;
106 const int kFramePointerRegCode = 29;
107 const int kLinkRegCode = 30;
108 const int kZeroRegCode = 31;
109 const int kSPRegInternalCode = 63;
110 const unsigned kRegCodeMask = 0x1f;
111 const unsigned kShiftAmountWRegMask = 0x1f;
112 const unsigned kShiftAmountXRegMask = 0x3f;
113 // Standard machine types defined by AAPCS64.
114 const unsigned kByteSize = 8;
115 const unsigned kByteSizeInBytes = kByteSize >> 3;
116 const unsigned kHalfWordSize = 16;
117 const unsigned kHalfWordSizeLog2 = 4;
118 const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3;
119 const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3;
120 const unsigned kWordSize = 32;
121 const unsigned kWordSizeLog2 = 5;
122 const unsigned kWordSizeInBytes = kWordSize >> 3;
123 const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3;
124 const unsigned kDoubleWordSize = 64;
125 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3;
126 const unsigned kQuadWordSize = 128;
127 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3;
128 const int kMaxLanesPerVector = 16;
129 
130 const unsigned kAddressTagOffset = 56;
131 const unsigned kAddressTagWidth = 8;
132 const uint64_t kAddressTagMask = ((UINT64_C(1) << kAddressTagWidth) - 1)
133  << kAddressTagOffset;
134 static_assert(kAddressTagMask == UINT64_C(0xff00000000000000),
135  "AddressTagMask must represent most-significant eight bits.");
136 
137 // AArch64 floating-point specifics. These match IEEE-754.
138 const unsigned kDoubleMantissaBits = 52;
139 const unsigned kDoubleExponentBits = 11;
140 const unsigned kDoubleExponentBias = 1023;
141 const unsigned kFloatMantissaBits = 23;
142 const unsigned kFloatExponentBits = 8;
143 const unsigned kFloatExponentBias = 127;
144 const unsigned kFloat16MantissaBits = 10;
145 const unsigned kFloat16ExponentBits = 5;
146 const unsigned kFloat16ExponentBias = 15;
147 
148 // Actual value of root register is offset from the root array's start
149 // to take advantage of negative displacement values.
150 // TODO(sigurds): Choose best value.
151 constexpr int kRootRegisterBias = 256;
152 
153 typedef uint16_t float16;
154 
155 #define INSTRUCTION_FIELDS_LIST(V_) \
156  /* Register fields */ \
157  V_(Rd, 4, 0, Bits) /* Destination register. */ \
158  V_(Rn, 9, 5, Bits) /* First source register. */ \
159  V_(Rm, 20, 16, Bits) /* Second source register. */ \
160  V_(Ra, 14, 10, Bits) /* Third source register. */ \
161  V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \
162  V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
163  /* store second source. */ \
164  V_(Rs, 20, 16, Bits) /* Store-exclusive status */ \
165  V_(PrefetchMode, 4, 0, Bits) \
166  \
167  /* Common bits */ \
168  V_(SixtyFourBits, 31, 31, Bits) \
169  V_(FlagsUpdate, 29, 29, Bits) \
170  \
171  /* PC relative addressing */ \
172  V_(ImmPCRelHi, 23, 5, SignedBits) \
173  V_(ImmPCRelLo, 30, 29, Bits) \
174  \
175  /* Add/subtract/logical shift register */ \
176  V_(ShiftDP, 23, 22, Bits) \
177  V_(ImmDPShift, 15, 10, Bits) \
178  \
179  /* Add/subtract immediate */ \
180  V_(ImmAddSub, 21, 10, Bits) \
181  V_(ShiftAddSub, 23, 22, Bits) \
182  \
183  /* Add/subtract extend */ \
184  V_(ImmExtendShift, 12, 10, Bits) \
185  V_(ExtendMode, 15, 13, Bits) \
186  \
187  /* Move wide */ \
188  V_(ImmMoveWide, 20, 5, Bits) \
189  V_(ShiftMoveWide, 22, 21, Bits) \
190  \
191  /* Logical immediate, bitfield and extract */ \
192  V_(BitN, 22, 22, Bits) \
193  V_(ImmRotate, 21, 16, Bits) \
194  V_(ImmSetBits, 15, 10, Bits) \
195  V_(ImmR, 21, 16, Bits) \
196  V_(ImmS, 15, 10, Bits) \
197  \
198  /* Test and branch immediate */ \
199  V_(ImmTestBranch, 18, 5, SignedBits) \
200  V_(ImmTestBranchBit40, 23, 19, Bits) \
201  V_(ImmTestBranchBit5, 31, 31, Bits) \
202  \
203  /* Conditionals */ \
204  V_(Condition, 15, 12, Bits) \
205  V_(ConditionBranch, 3, 0, Bits) \
206  V_(Nzcv, 3, 0, Bits) \
207  V_(ImmCondCmp, 20, 16, Bits) \
208  V_(ImmCondBranch, 23, 5, SignedBits) \
209  \
210  /* Floating point */ \
211  V_(FPType, 23, 22, Bits) \
212  V_(ImmFP, 20, 13, Bits) \
213  V_(FPScale, 15, 10, Bits) \
214  \
215  /* Load Store */ \
216  V_(ImmLS, 20, 12, SignedBits) \
217  V_(ImmLSUnsigned, 21, 10, Bits) \
218  V_(ImmLSPair, 21, 15, SignedBits) \
219  V_(ImmShiftLS, 12, 12, Bits) \
220  V_(LSOpc, 23, 22, Bits) \
221  V_(LSVector, 26, 26, Bits) \
222  V_(LSSize, 31, 30, Bits) \
223  \
224  /* NEON generic fields */ \
225  V_(NEONQ, 30, 30, Bits) \
226  V_(NEONSize, 23, 22, Bits) \
227  V_(NEONLSSize, 11, 10, Bits) \
228  V_(NEONS, 12, 12, Bits) \
229  V_(NEONL, 21, 21, Bits) \
230  V_(NEONM, 20, 20, Bits) \
231  V_(NEONH, 11, 11, Bits) \
232  V_(ImmNEONExt, 14, 11, Bits) \
233  V_(ImmNEON5, 20, 16, Bits) \
234  V_(ImmNEON4, 14, 11, Bits) \
235  \
236  /* Other immediates */ \
237  V_(ImmUncondBranch, 25, 0, SignedBits) \
238  V_(ImmCmpBranch, 23, 5, SignedBits) \
239  V_(ImmLLiteral, 23, 5, SignedBits) \
240  V_(ImmException, 20, 5, Bits) \
241  V_(ImmHint, 11, 5, Bits) \
242  V_(ImmBarrierDomain, 11, 10, Bits) \
243  V_(ImmBarrierType, 9, 8, Bits) \
244  \
245  /* System (MRS, MSR) */ \
246  V_(ImmSystemRegister, 19, 5, Bits) \
247  V_(SysO0, 19, 19, Bits) \
248  V_(SysOp1, 18, 16, Bits) \
249  V_(SysOp2, 7, 5, Bits) \
250  V_(CRn, 15, 12, Bits) \
251  V_(CRm, 11, 8, Bits) \
252  \
253  /* Load-/store-exclusive */ \
254  V_(LoadStoreXLoad, 22, 22, Bits) \
255  V_(LoadStoreXNotExclusive, 23, 23, Bits) \
256  V_(LoadStoreXAcquireRelease, 15, 15, Bits) \
257  V_(LoadStoreXSizeLog2, 31, 30, Bits) \
258  V_(LoadStoreXPair, 21, 21, Bits) \
259  \
260  /* NEON load/store */ \
261  V_(NEONLoad, 22, 22, Bits) \
262  \
263  /* NEON Modified Immediate fields */ \
264  V_(ImmNEONabc, 18, 16, Bits) \
265  V_(ImmNEONdefgh, 9, 5, Bits) \
266  V_(NEONModImmOp, 29, 29, Bits) \
267  V_(NEONCmode, 15, 12, Bits) \
268  \
269  /* NEON Shift Immediate fields */ \
270  V_(ImmNEONImmhImmb, 22, 16, Bits) \
271  V_(ImmNEONImmh, 22, 19, Bits) \
272  V_(ImmNEONImmb, 18, 16, Bits)
273 
274 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
275 /* NZCV */ \
276 V_(Flags, 31, 28, Bits, uint32_t) \
277 V_(N, 31, 31, Bits, bool) \
278 V_(Z, 30, 30, Bits, bool) \
279 V_(C, 29, 29, Bits, bool) \
280 V_(V, 28, 28, Bits, bool) \
281 M_(NZCV, Flags_mask) \
282  \
283 /* FPCR */ \
284 V_(AHP, 26, 26, Bits, bool) \
285 V_(DN, 25, 25, Bits, bool) \
286 V_(FZ, 24, 24, Bits, bool) \
287 V_(RMode, 23, 22, Bits, FPRounding) \
288 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
289 
290 
291 // Fields offsets.
292 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2) \
293  const int Name##_offset = LowBit; \
294  const int Name##_width = HighBit - LowBit + 1; \
295  const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
296 #define DECLARE_INSTRUCTION_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1) \
297  DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2)
298 INSTRUCTION_FIELDS_LIST(DECLARE_INSTRUCTION_FIELDS_OFFSETS)
299 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
300 #undef DECLARE_FIELDS_OFFSETS
301 #undef DECLARE_INSTRUCTION_FIELDS_OFFSETS
302 
303 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
304 // from ImmPCRelLo and ImmPCRelHi.
305 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
306 
307 // Condition codes.
308 enum Condition {
309  eq = 0,
310  ne = 1,
311  hs = 2, cs = hs,
312  lo = 3, cc = lo,
313  mi = 4,
314  pl = 5,
315  vs = 6,
316  vc = 7,
317  hi = 8,
318  ls = 9,
319  ge = 10,
320  lt = 11,
321  gt = 12,
322  le = 13,
323  al = 14,
324  nv = 15 // Behaves as always/al.
325 };
326 
327 inline Condition NegateCondition(Condition cond) {
328  // Conditions al and nv behave identically, as "always true". They can't be
329  // inverted, because there is no never condition.
330  DCHECK((cond != al) && (cond != nv));
331  return static_cast<Condition>(cond ^ 1);
332 }
333 
334 enum FlagsUpdate {
335  SetFlags = 1,
336  LeaveFlags = 0
337 };
338 
339 enum StatusFlags {
340  NoFlag = 0,
341 
342  // Derive the flag combinations from the system register bit descriptions.
343  NFlag = N_mask,
344  ZFlag = Z_mask,
345  CFlag = C_mask,
346  VFlag = V_mask,
347  NZFlag = NFlag | ZFlag,
348  NCFlag = NFlag | CFlag,
349  NVFlag = NFlag | VFlag,
350  ZCFlag = ZFlag | CFlag,
351  ZVFlag = ZFlag | VFlag,
352  CVFlag = CFlag | VFlag,
353  NZCFlag = NFlag | ZFlag | CFlag,
354  NZVFlag = NFlag | ZFlag | VFlag,
355  NCVFlag = NFlag | CFlag | VFlag,
356  ZCVFlag = ZFlag | CFlag | VFlag,
357  NZCVFlag = NFlag | ZFlag | CFlag | VFlag,
358 
359  // Floating-point comparison results.
360  FPEqualFlag = ZCFlag,
361  FPLessThanFlag = NFlag,
362  FPGreaterThanFlag = CFlag,
363  FPUnorderedFlag = CVFlag
364 };
365 
366 enum Shift {
367  NO_SHIFT = -1,
368  LSL = 0x0,
369  LSR = 0x1,
370  ASR = 0x2,
371  ROR = 0x3,
372  MSL = 0x4
373 };
374 
375 enum Extend {
376  NO_EXTEND = -1,
377  UXTB = 0,
378  UXTH = 1,
379  UXTW = 2,
380  UXTX = 3,
381  SXTB = 4,
382  SXTH = 5,
383  SXTW = 6,
384  SXTX = 7
385 };
386 
387 enum SystemHint {
388  NOP = 0,
389  YIELD = 1,
390  WFE = 2,
391  WFI = 3,
392  SEV = 4,
393  SEVL = 5,
394  CSDB = 20
395 };
396 
397 enum BarrierDomain {
398  OuterShareable = 0,
399  NonShareable = 1,
400  InnerShareable = 2,
401  FullSystem = 3
402 };
403 
404 enum BarrierType {
405  BarrierOther = 0,
406  BarrierReads = 1,
407  BarrierWrites = 2,
408  BarrierAll = 3
409 };
410 
411 // System/special register names.
412 // This information is not encoded as one field but as the concatenation of
413 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
414 enum SystemRegister {
415  NZCV = ((0x1 << SysO0_offset) |
416  (0x3 << SysOp1_offset) |
417  (0x4 << CRn_offset) |
418  (0x2 << CRm_offset) |
419  (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset,
420  FPCR = ((0x1 << SysO0_offset) |
421  (0x3 << SysOp1_offset) |
422  (0x4 << CRn_offset) |
423  (0x4 << CRm_offset) |
424  (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset
425 };
426 
427 // Instruction enumerations.
428 //
429 // These are the masks that define a class of instructions, and the list of
430 // instructions within each class. Each enumeration has a Fixed, FMask and
431 // Mask value.
432 //
433 // Fixed: The fixed bits in this instruction class.
434 // FMask: The mask used to extract the fixed bits in the class.
435 // Mask: The mask used to identify the instructions within a class.
436 //
437 // The enumerations can be used like this:
438 //
439 // DCHECK(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
440 // switch(instr->Mask(PCRelAddressingMask)) {
441 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
442 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
443 // default: printf("Unknown instruction\n");
444 // }
445 
446 // Used to corrupt encodings by setting all bits when orred. Although currently
447 // unallocated in AArch64, this encoding is not guaranteed to be undefined
448 // indefinitely.
449 const uint32_t kUnallocatedInstruction = 0xffffffff;
450 
451 // Generic fields.
452 enum GenericInstrField : uint32_t {
453  SixtyFourBits = 0x80000000,
454  ThirtyTwoBits = 0x00000000,
455  FP32 = 0x00000000,
456  FP64 = 0x00400000
457 };
458 
459 enum NEONFormatField : uint32_t {
460  NEONFormatFieldMask = 0x40C00000,
461  NEON_Q = 0x40000000,
462  NEON_8B = 0x00000000,
463  NEON_16B = NEON_8B | NEON_Q,
464  NEON_4H = 0x00400000,
465  NEON_8H = NEON_4H | NEON_Q,
466  NEON_2S = 0x00800000,
467  NEON_4S = NEON_2S | NEON_Q,
468  NEON_1D = 0x00C00000,
469  NEON_2D = 0x00C00000 | NEON_Q
470 };
471 
472 enum NEONFPFormatField : uint32_t {
473  NEONFPFormatFieldMask = 0x40400000,
474  NEON_FP_2S = FP32,
475  NEON_FP_4S = FP32 | NEON_Q,
476  NEON_FP_2D = FP64 | NEON_Q
477 };
478 
479 enum NEONLSFormatField : uint32_t {
480  NEONLSFormatFieldMask = 0x40000C00,
481  LS_NEON_8B = 0x00000000,
482  LS_NEON_16B = LS_NEON_8B | NEON_Q,
483  LS_NEON_4H = 0x00000400,
484  LS_NEON_8H = LS_NEON_4H | NEON_Q,
485  LS_NEON_2S = 0x00000800,
486  LS_NEON_4S = LS_NEON_2S | NEON_Q,
487  LS_NEON_1D = 0x00000C00,
488  LS_NEON_2D = LS_NEON_1D | NEON_Q
489 };
490 
491 enum NEONScalarFormatField : uint32_t {
492  NEONScalarFormatFieldMask = 0x00C00000,
493  NEONScalar = 0x10000000,
494  NEON_B = 0x00000000,
495  NEON_H = 0x00400000,
496  NEON_S = 0x00800000,
497  NEON_D = 0x00C00000
498 };
499 
500 // PC relative addressing.
501 enum PCRelAddressingOp : uint32_t {
502  PCRelAddressingFixed = 0x10000000,
503  PCRelAddressingFMask = 0x1F000000,
504  PCRelAddressingMask = 0x9F000000,
505  ADR = PCRelAddressingFixed | 0x00000000,
506  ADRP = PCRelAddressingFixed | 0x80000000
507 };
508 
509 // Add/sub (immediate, shifted and extended.)
510 const int kSFOffset = 31;
511 enum AddSubOp : uint32_t {
512  AddSubOpMask = 0x60000000,
513  AddSubSetFlagsBit = 0x20000000,
514  ADD = 0x00000000,
515  ADDS = ADD | AddSubSetFlagsBit,
516  SUB = 0x40000000,
517  SUBS = SUB | AddSubSetFlagsBit
518 };
519 
520 #define ADD_SUB_OP_LIST(V) \
521  V(ADD), \
522  V(ADDS), \
523  V(SUB), \
524  V(SUBS)
525 
526 enum AddSubImmediateOp : uint32_t {
527  AddSubImmediateFixed = 0x11000000,
528  AddSubImmediateFMask = 0x1F000000,
529  AddSubImmediateMask = 0xFF000000,
530  #define ADD_SUB_IMMEDIATE(A) \
531  A##_w_imm = AddSubImmediateFixed | A, \
532  A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
533  ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
534  #undef ADD_SUB_IMMEDIATE
535 };
536 
537 enum AddSubShiftedOp : uint32_t {
538  AddSubShiftedFixed = 0x0B000000,
539  AddSubShiftedFMask = 0x1F200000,
540  AddSubShiftedMask = 0xFF200000,
541  #define ADD_SUB_SHIFTED(A) \
542  A##_w_shift = AddSubShiftedFixed | A, \
543  A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
544  ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
545  #undef ADD_SUB_SHIFTED
546 };
547 
548 enum AddSubExtendedOp : uint32_t {
549  AddSubExtendedFixed = 0x0B200000,
550  AddSubExtendedFMask = 0x1F200000,
551  AddSubExtendedMask = 0xFFE00000,
552  #define ADD_SUB_EXTENDED(A) \
553  A##_w_ext = AddSubExtendedFixed | A, \
554  A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
555  ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
556  #undef ADD_SUB_EXTENDED
557 };
558 
559 // Add/sub with carry.
560 enum AddSubWithCarryOp : uint32_t {
561  AddSubWithCarryFixed = 0x1A000000,
562  AddSubWithCarryFMask = 0x1FE00000,
563  AddSubWithCarryMask = 0xFFE0FC00,
564  ADC_w = AddSubWithCarryFixed | ADD,
565  ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits,
566  ADC = ADC_w,
567  ADCS_w = AddSubWithCarryFixed | ADDS,
568  ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
569  SBC_w = AddSubWithCarryFixed | SUB,
570  SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits,
571  SBC = SBC_w,
572  SBCS_w = AddSubWithCarryFixed | SUBS,
573  SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits
574 };
575 
576 
577 // Logical (immediate and shifted register).
578 enum LogicalOp : uint32_t {
579  LogicalOpMask = 0x60200000,
580  NOT = 0x00200000,
581  AND = 0x00000000,
582  BIC = AND | NOT,
583  ORR = 0x20000000,
584  ORN = ORR | NOT,
585  EOR = 0x40000000,
586  EON = EOR | NOT,
587  ANDS = 0x60000000,
588  BICS = ANDS | NOT
589 };
590 
591 // Logical immediate.
592 enum LogicalImmediateOp : uint32_t {
593  LogicalImmediateFixed = 0x12000000,
594  LogicalImmediateFMask = 0x1F800000,
595  LogicalImmediateMask = 0xFF800000,
596  AND_w_imm = LogicalImmediateFixed | AND,
597  AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits,
598  ORR_w_imm = LogicalImmediateFixed | ORR,
599  ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
600  EOR_w_imm = LogicalImmediateFixed | EOR,
601  EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
602  ANDS_w_imm = LogicalImmediateFixed | ANDS,
603  ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
604 };
605 
606 // Logical shifted register.
607 enum LogicalShiftedOp : uint32_t {
608  LogicalShiftedFixed = 0x0A000000,
609  LogicalShiftedFMask = 0x1F000000,
610  LogicalShiftedMask = 0xFF200000,
611  AND_w = LogicalShiftedFixed | AND,
612  AND_x = LogicalShiftedFixed | AND | SixtyFourBits,
613  AND_shift = AND_w,
614  BIC_w = LogicalShiftedFixed | BIC,
615  BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
616  BIC_shift = BIC_w,
617  ORR_w = LogicalShiftedFixed | ORR,
618  ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
619  ORR_shift = ORR_w,
620  ORN_w = LogicalShiftedFixed | ORN,
621  ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
622  ORN_shift = ORN_w,
623  EOR_w = LogicalShiftedFixed | EOR,
624  EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
625  EOR_shift = EOR_w,
626  EON_w = LogicalShiftedFixed | EON,
627  EON_x = LogicalShiftedFixed | EON | SixtyFourBits,
628  EON_shift = EON_w,
629  ANDS_w = LogicalShiftedFixed | ANDS,
630  ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
631  ANDS_shift = ANDS_w,
632  BICS_w = LogicalShiftedFixed | BICS,
633  BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
634  BICS_shift = BICS_w
635 };
636 
637 // Move wide immediate.
638 enum MoveWideImmediateOp : uint32_t {
639  MoveWideImmediateFixed = 0x12800000,
640  MoveWideImmediateFMask = 0x1F800000,
641  MoveWideImmediateMask = 0xFF800000,
642  MOVN = 0x00000000,
643  MOVZ = 0x40000000,
644  MOVK = 0x60000000,
645  MOVN_w = MoveWideImmediateFixed | MOVN,
646  MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
647  MOVZ_w = MoveWideImmediateFixed | MOVZ,
648  MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
649  MOVK_w = MoveWideImmediateFixed | MOVK,
650  MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
651 };
652 
653 // Bitfield.
654 const int kBitfieldNOffset = 22;
655 enum BitfieldOp : uint32_t {
656  BitfieldFixed = 0x13000000,
657  BitfieldFMask = 0x1F800000,
658  BitfieldMask = 0xFF800000,
659  SBFM_w = BitfieldFixed | 0x00000000,
660  SBFM_x = BitfieldFixed | 0x80000000,
661  SBFM = SBFM_w,
662  BFM_w = BitfieldFixed | 0x20000000,
663  BFM_x = BitfieldFixed | 0xA0000000,
664  BFM = BFM_w,
665  UBFM_w = BitfieldFixed | 0x40000000,
666  UBFM_x = BitfieldFixed | 0xC0000000,
667  UBFM = UBFM_w
668  // Bitfield N field.
669 };
670 
671 // Extract.
672 enum ExtractOp : uint32_t {
673  ExtractFixed = 0x13800000,
674  ExtractFMask = 0x1F800000,
675  ExtractMask = 0xFFA00000,
676  EXTR_w = ExtractFixed | 0x00000000,
677  EXTR_x = ExtractFixed | 0x80000000,
678  EXTR = EXTR_w
679 };
680 
681 // Unconditional branch.
682 enum UnconditionalBranchOp : uint32_t {
683  UnconditionalBranchFixed = 0x14000000,
684  UnconditionalBranchFMask = 0x7C000000,
685  UnconditionalBranchMask = 0xFC000000,
686  B = UnconditionalBranchFixed | 0x00000000,
687  BL = UnconditionalBranchFixed | 0x80000000
688 };
689 
690 // Unconditional branch to register.
691 enum UnconditionalBranchToRegisterOp : uint32_t {
692  UnconditionalBranchToRegisterFixed = 0xD6000000,
693  UnconditionalBranchToRegisterFMask = 0xFE000000,
694  UnconditionalBranchToRegisterMask = 0xFFFFFC1F,
695  BR = UnconditionalBranchToRegisterFixed | 0x001F0000,
696  BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
697  RET = UnconditionalBranchToRegisterFixed | 0x005F0000
698 };
699 
700 // Compare and branch.
701 enum CompareBranchOp : uint32_t {
702  CompareBranchFixed = 0x34000000,
703  CompareBranchFMask = 0x7E000000,
704  CompareBranchMask = 0xFF000000,
705  CBZ_w = CompareBranchFixed | 0x00000000,
706  CBZ_x = CompareBranchFixed | 0x80000000,
707  CBZ = CBZ_w,
708  CBNZ_w = CompareBranchFixed | 0x01000000,
709  CBNZ_x = CompareBranchFixed | 0x81000000,
710  CBNZ = CBNZ_w
711 };
712 
713 // Test and branch.
714 enum TestBranchOp : uint32_t {
715  TestBranchFixed = 0x36000000,
716  TestBranchFMask = 0x7E000000,
717  TestBranchMask = 0x7F000000,
718  TBZ = TestBranchFixed | 0x00000000,
719  TBNZ = TestBranchFixed | 0x01000000
720 };
721 
722 // Conditional branch.
723 enum ConditionalBranchOp : uint32_t {
724  ConditionalBranchFixed = 0x54000000,
725  ConditionalBranchFMask = 0xFE000000,
726  ConditionalBranchMask = 0xFF000010,
727  B_cond = ConditionalBranchFixed | 0x00000000
728 };
729 
730 // System.
731 // System instruction encoding is complicated because some instructions use op
732 // and CR fields to encode parameters. To handle this cleanly, the system
733 // instructions are split into more than one enum.
734 
735 enum SystemOp : uint32_t {
736  SystemFixed = 0xD5000000,
737  SystemFMask = 0xFFC00000
738 };
739 
740 enum SystemSysRegOp : uint32_t {
741  SystemSysRegFixed = 0xD5100000,
742  SystemSysRegFMask = 0xFFD00000,
743  SystemSysRegMask = 0xFFF00000,
744  MRS = SystemSysRegFixed | 0x00200000,
745  MSR = SystemSysRegFixed | 0x00000000
746 };
747 
748 enum SystemHintOp : uint32_t {
749  SystemHintFixed = 0xD503201F,
750  SystemHintFMask = 0xFFFFF01F,
751  SystemHintMask = 0xFFFFF01F,
752  HINT = SystemHintFixed | 0x00000000
753 };
754 
755 // Exception.
756 enum ExceptionOp : uint32_t {
757  ExceptionFixed = 0xD4000000,
758  ExceptionFMask = 0xFF000000,
759  ExceptionMask = 0xFFE0001F,
760  HLT = ExceptionFixed | 0x00400000,
761  BRK = ExceptionFixed | 0x00200000,
762  SVC = ExceptionFixed | 0x00000001,
763  HVC = ExceptionFixed | 0x00000002,
764  SMC = ExceptionFixed | 0x00000003,
765  DCPS1 = ExceptionFixed | 0x00A00001,
766  DCPS2 = ExceptionFixed | 0x00A00002,
767  DCPS3 = ExceptionFixed | 0x00A00003
768 };
769 // Code used to spot hlt instructions that should not be hit.
770 const int kHltBadCode = 0xbad;
771 
772 enum MemBarrierOp : uint32_t {
773  MemBarrierFixed = 0xD503309F,
774  MemBarrierFMask = 0xFFFFF09F,
775  MemBarrierMask = 0xFFFFF0FF,
776  DSB = MemBarrierFixed | 0x00000000,
777  DMB = MemBarrierFixed | 0x00000020,
778  ISB = MemBarrierFixed | 0x00000040
779 };
780 
781 // Any load or store (including pair).
782 enum LoadStoreAnyOp : uint32_t {
783  LoadStoreAnyFMask = 0x0a000000,
784  LoadStoreAnyFixed = 0x08000000
785 };
786 
787 // Any load pair or store pair.
788 enum LoadStorePairAnyOp : uint32_t {
789  LoadStorePairAnyFMask = 0x3a000000,
790  LoadStorePairAnyFixed = 0x28000000
791 };
792 
793 #define LOAD_STORE_PAIR_OP_LIST(V) \
794  V(STP, w, 0x00000000) \
795  , V(LDP, w, 0x00400000), V(LDPSW, x, 0x40400000), V(STP, x, 0x80000000), \
796  V(LDP, x, 0x80400000), V(STP, s, 0x04000000), V(LDP, s, 0x04400000), \
797  V(STP, d, 0x44000000), V(LDP, d, 0x44400000), V(STP, q, 0x84000000), \
798  V(LDP, q, 0x84400000)
799 
800 // Load/store pair (post, pre and offset.)
801 enum LoadStorePairOp : uint32_t {
802  LoadStorePairMask = 0xC4400000,
803  LoadStorePairLBit = 1 << 22,
804  #define LOAD_STORE_PAIR(A, B, C) \
805  A##_##B = C
806  LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
807  #undef LOAD_STORE_PAIR
808 };
809 
810 enum LoadStorePairPostIndexOp : uint32_t {
811  LoadStorePairPostIndexFixed = 0x28800000,
812  LoadStorePairPostIndexFMask = 0x3B800000,
813  LoadStorePairPostIndexMask = 0xFFC00000,
814  #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \
815  A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
816  LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
817  #undef LOAD_STORE_PAIR_POST_INDEX
818 };
819 
820 enum LoadStorePairPreIndexOp : uint32_t {
821  LoadStorePairPreIndexFixed = 0x29800000,
822  LoadStorePairPreIndexFMask = 0x3B800000,
823  LoadStorePairPreIndexMask = 0xFFC00000,
824  #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \
825  A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
826  LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
827  #undef LOAD_STORE_PAIR_PRE_INDEX
828 };
829 
830 enum LoadStorePairOffsetOp : uint32_t {
831  LoadStorePairOffsetFixed = 0x29000000,
832  LoadStorePairOffsetFMask = 0x3B800000,
833  LoadStorePairOffsetMask = 0xFFC00000,
834  #define LOAD_STORE_PAIR_OFFSET(A, B, C) \
835  A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
836  LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
837  #undef LOAD_STORE_PAIR_OFFSET
838 };
839 
840 // Load literal.
841 enum LoadLiteralOp : uint32_t {
842  LoadLiteralFixed = 0x18000000,
843  LoadLiteralFMask = 0x3B000000,
844  LoadLiteralMask = 0xFF000000,
845  LDR_w_lit = LoadLiteralFixed | 0x00000000,
846  LDR_x_lit = LoadLiteralFixed | 0x40000000,
847  LDRSW_x_lit = LoadLiteralFixed | 0x80000000,
848  PRFM_lit = LoadLiteralFixed | 0xC0000000,
849  LDR_s_lit = LoadLiteralFixed | 0x04000000,
850  LDR_d_lit = LoadLiteralFixed | 0x44000000
851 };
852 
853 // clang-format off
854 
855 #define LOAD_STORE_OP_LIST(V) \
856  V(ST, RB, w, 0x00000000), \
857  V(ST, RH, w, 0x40000000), \
858  V(ST, R, w, 0x80000000), \
859  V(ST, R, x, 0xC0000000), \
860  V(LD, RB, w, 0x00400000), \
861  V(LD, RH, w, 0x40400000), \
862  V(LD, R, w, 0x80400000), \
863  V(LD, R, x, 0xC0400000), \
864  V(LD, RSB, x, 0x00800000), \
865  V(LD, RSH, x, 0x40800000), \
866  V(LD, RSW, x, 0x80800000), \
867  V(LD, RSB, w, 0x00C00000), \
868  V(LD, RSH, w, 0x40C00000), \
869  V(ST, R, b, 0x04000000), \
870  V(ST, R, h, 0x44000000), \
871  V(ST, R, s, 0x84000000), \
872  V(ST, R, d, 0xC4000000), \
873  V(ST, R, q, 0x04800000), \
874  V(LD, R, b, 0x04400000), \
875  V(LD, R, h, 0x44400000), \
876  V(LD, R, s, 0x84400000), \
877  V(LD, R, d, 0xC4400000), \
878  V(LD, R, q, 0x04C00000)
879 
880 // clang-format on
881 
882 // Load/store unscaled offset.
883 enum LoadStoreUnscaledOffsetOp : uint32_t {
884  LoadStoreUnscaledOffsetFixed = 0x38000000,
885  LoadStoreUnscaledOffsetFMask = 0x3B200C00,
886  LoadStoreUnscaledOffsetMask = 0xFFE00C00,
887  #define LOAD_STORE_UNSCALED(A, B, C, D) \
888  A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
889  LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
890  #undef LOAD_STORE_UNSCALED
891 };
892 
893 // Load/store (post, pre, offset and unsigned.)
894 enum LoadStoreOp : uint32_t {
895  LoadStoreMask = 0xC4C00000,
896 #define LOAD_STORE(A, B, C, D) A##B##_##C = D
897  LOAD_STORE_OP_LIST(LOAD_STORE),
898 #undef LOAD_STORE
899  PRFM = 0xC0800000
900 };
901 
902 // Load/store post index.
903 enum LoadStorePostIndex : uint32_t {
904  LoadStorePostIndexFixed = 0x38000400,
905  LoadStorePostIndexFMask = 0x3B200C00,
906  LoadStorePostIndexMask = 0xFFE00C00,
907  #define LOAD_STORE_POST_INDEX(A, B, C, D) \
908  A##B##_##C##_post = LoadStorePostIndexFixed | D
909  LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
910  #undef LOAD_STORE_POST_INDEX
911 };
912 
913 // Load/store pre index.
914 enum LoadStorePreIndex : uint32_t {
915  LoadStorePreIndexFixed = 0x38000C00,
916  LoadStorePreIndexFMask = 0x3B200C00,
917  LoadStorePreIndexMask = 0xFFE00C00,
918  #define LOAD_STORE_PRE_INDEX(A, B, C, D) \
919  A##B##_##C##_pre = LoadStorePreIndexFixed | D
920  LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
921  #undef LOAD_STORE_PRE_INDEX
922 };
923 
924 // Load/store unsigned offset.
925 enum LoadStoreUnsignedOffset : uint32_t {
926  LoadStoreUnsignedOffsetFixed = 0x39000000,
927  LoadStoreUnsignedOffsetFMask = 0x3B000000,
928  LoadStoreUnsignedOffsetMask = 0xFFC00000,
929  PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM,
930  #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
931  A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
932  LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
933  #undef LOAD_STORE_UNSIGNED_OFFSET
934 };
935 
936 // Load/store register offset.
937 enum LoadStoreRegisterOffset : uint32_t {
938  LoadStoreRegisterOffsetFixed = 0x38200800,
939  LoadStoreRegisterOffsetFMask = 0x3B200C00,
940  LoadStoreRegisterOffsetMask = 0xFFE00C00,
941  PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM,
942  #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
943  A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
944  LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
945  #undef LOAD_STORE_REGISTER_OFFSET
946 };
947 
948 // Load/store acquire/release.
949 enum LoadStoreAcquireReleaseOp : uint32_t {
950  LoadStoreAcquireReleaseFixed = 0x08000000,
951  LoadStoreAcquireReleaseFMask = 0x3F000000,
952  LoadStoreAcquireReleaseMask = 0xCFC08000,
953  STLXR_b = LoadStoreAcquireReleaseFixed | 0x00008000,
954  LDAXR_b = LoadStoreAcquireReleaseFixed | 0x00408000,
955  STLR_b = LoadStoreAcquireReleaseFixed | 0x00808000,
956  LDAR_b = LoadStoreAcquireReleaseFixed | 0x00C08000,
957  STLXR_h = LoadStoreAcquireReleaseFixed | 0x40008000,
958  LDAXR_h = LoadStoreAcquireReleaseFixed | 0x40408000,
959  STLR_h = LoadStoreAcquireReleaseFixed | 0x40808000,
960  LDAR_h = LoadStoreAcquireReleaseFixed | 0x40C08000,
961  STLXR_w = LoadStoreAcquireReleaseFixed | 0x80008000,
962  LDAXR_w = LoadStoreAcquireReleaseFixed | 0x80408000,
963  STLR_w = LoadStoreAcquireReleaseFixed | 0x80808000,
964  LDAR_w = LoadStoreAcquireReleaseFixed | 0x80C08000,
965  STLXR_x = LoadStoreAcquireReleaseFixed | 0xC0008000,
966  LDAXR_x = LoadStoreAcquireReleaseFixed | 0xC0408000,
967  STLR_x = LoadStoreAcquireReleaseFixed | 0xC0808000,
968  LDAR_x = LoadStoreAcquireReleaseFixed | 0xC0C08000,
969 };
970 
971 // Conditional compare.
972 enum ConditionalCompareOp : uint32_t {
973  ConditionalCompareMask = 0x60000000,
974  CCMN = 0x20000000,
975  CCMP = 0x60000000
976 };
977 
978 // Conditional compare register.
979 enum ConditionalCompareRegisterOp : uint32_t {
980  ConditionalCompareRegisterFixed = 0x1A400000,
981  ConditionalCompareRegisterFMask = 0x1FE00800,
982  ConditionalCompareRegisterMask = 0xFFE00C10,
983  CCMN_w = ConditionalCompareRegisterFixed | CCMN,
984  CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
985  CCMP_w = ConditionalCompareRegisterFixed | CCMP,
986  CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
987 };
988 
989 // Conditional compare immediate.
990 enum ConditionalCompareImmediateOp : uint32_t {
991  ConditionalCompareImmediateFixed = 0x1A400800,
992  ConditionalCompareImmediateFMask = 0x1FE00800,
993  ConditionalCompareImmediateMask = 0xFFE00C10,
994  CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
995  CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
996  CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
997  CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
998 };
999 
1000 // Conditional select.
1001 enum ConditionalSelectOp : uint32_t {
1002  ConditionalSelectFixed = 0x1A800000,
1003  ConditionalSelectFMask = 0x1FE00000,
1004  ConditionalSelectMask = 0xFFE00C00,
1005  CSEL_w = ConditionalSelectFixed | 0x00000000,
1006  CSEL_x = ConditionalSelectFixed | 0x80000000,
1007  CSEL = CSEL_w,
1008  CSINC_w = ConditionalSelectFixed | 0x00000400,
1009  CSINC_x = ConditionalSelectFixed | 0x80000400,
1010  CSINC = CSINC_w,
1011  CSINV_w = ConditionalSelectFixed | 0x40000000,
1012  CSINV_x = ConditionalSelectFixed | 0xC0000000,
1013  CSINV = CSINV_w,
1014  CSNEG_w = ConditionalSelectFixed | 0x40000400,
1015  CSNEG_x = ConditionalSelectFixed | 0xC0000400,
1016  CSNEG = CSNEG_w
1017 };
1018 
1019 // Data processing 1 source.
1020 enum DataProcessing1SourceOp : uint32_t {
1021  DataProcessing1SourceFixed = 0x5AC00000,
1022  DataProcessing1SourceFMask = 0x5FE00000,
1023  DataProcessing1SourceMask = 0xFFFFFC00,
1024  RBIT = DataProcessing1SourceFixed | 0x00000000,
1025  RBIT_w = RBIT,
1026  RBIT_x = RBIT | SixtyFourBits,
1027  REV16 = DataProcessing1SourceFixed | 0x00000400,
1028  REV16_w = REV16,
1029  REV16_x = REV16 | SixtyFourBits,
1030  REV = DataProcessing1SourceFixed | 0x00000800,
1031  REV_w = REV,
1032  REV32_x = REV | SixtyFourBits,
1033  REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
1034  CLZ = DataProcessing1SourceFixed | 0x00001000,
1035  CLZ_w = CLZ,
1036  CLZ_x = CLZ | SixtyFourBits,
1037  CLS = DataProcessing1SourceFixed | 0x00001400,
1038  CLS_w = CLS,
1039  CLS_x = CLS | SixtyFourBits
1040 };
1041 
1042 // Data processing 2 source.
1043 enum DataProcessing2SourceOp : uint32_t {
1044  DataProcessing2SourceFixed = 0x1AC00000,
1045  DataProcessing2SourceFMask = 0x5FE00000,
1046  DataProcessing2SourceMask = 0xFFE0FC00,
1047  UDIV_w = DataProcessing2SourceFixed | 0x00000800,
1048  UDIV_x = DataProcessing2SourceFixed | 0x80000800,
1049  UDIV = UDIV_w,
1050  SDIV_w = DataProcessing2SourceFixed | 0x00000C00,
1051  SDIV_x = DataProcessing2SourceFixed | 0x80000C00,
1052  SDIV = SDIV_w,
1053  LSLV_w = DataProcessing2SourceFixed | 0x00002000,
1054  LSLV_x = DataProcessing2SourceFixed | 0x80002000,
1055  LSLV = LSLV_w,
1056  LSRV_w = DataProcessing2SourceFixed | 0x00002400,
1057  LSRV_x = DataProcessing2SourceFixed | 0x80002400,
1058  LSRV = LSRV_w,
1059  ASRV_w = DataProcessing2SourceFixed | 0x00002800,
1060  ASRV_x = DataProcessing2SourceFixed | 0x80002800,
1061  ASRV = ASRV_w,
1062  RORV_w = DataProcessing2SourceFixed | 0x00002C00,
1063  RORV_x = DataProcessing2SourceFixed | 0x80002C00,
1064  RORV = RORV_w,
1065  CRC32B = DataProcessing2SourceFixed | 0x00004000,
1066  CRC32H = DataProcessing2SourceFixed | 0x00004400,
1067  CRC32W = DataProcessing2SourceFixed | 0x00004800,
1068  CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
1069  CRC32CB = DataProcessing2SourceFixed | 0x00005000,
1070  CRC32CH = DataProcessing2SourceFixed | 0x00005400,
1071  CRC32CW = DataProcessing2SourceFixed | 0x00005800,
1072  CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
1073 };
1074 
1075 // Data processing 3 source.
1076 enum DataProcessing3SourceOp : uint32_t {
1077  DataProcessing3SourceFixed = 0x1B000000,
1078  DataProcessing3SourceFMask = 0x1F000000,
1079  DataProcessing3SourceMask = 0xFFE08000,
1080  MADD_w = DataProcessing3SourceFixed | 0x00000000,
1081  MADD_x = DataProcessing3SourceFixed | 0x80000000,
1082  MADD = MADD_w,
1083  MSUB_w = DataProcessing3SourceFixed | 0x00008000,
1084  MSUB_x = DataProcessing3SourceFixed | 0x80008000,
1085  MSUB = MSUB_w,
1086  SMADDL_x = DataProcessing3SourceFixed | 0x80200000,
1087  SMSUBL_x = DataProcessing3SourceFixed | 0x80208000,
1088  SMULH_x = DataProcessing3SourceFixed | 0x80400000,
1089  UMADDL_x = DataProcessing3SourceFixed | 0x80A00000,
1090  UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000,
1091  UMULH_x = DataProcessing3SourceFixed | 0x80C00000
1092 };
1093 
1094 // Floating point compare.
1095 enum FPCompareOp : uint32_t {
1096  FPCompareFixed = 0x1E202000,
1097  FPCompareFMask = 0x5F203C00,
1098  FPCompareMask = 0xFFE0FC1F,
1099  FCMP_s = FPCompareFixed | 0x00000000,
1100  FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1101  FCMP = FCMP_s,
1102  FCMP_s_zero = FPCompareFixed | 0x00000008,
1103  FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1104  FCMP_zero = FCMP_s_zero,
1105  FCMPE_s = FPCompareFixed | 0x00000010,
1106  FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1107  FCMPE_s_zero = FPCompareFixed | 0x00000018,
1108  FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018
1109 };
1110 
1111 // Floating point conditional compare.
1112 enum FPConditionalCompareOp : uint32_t {
1113  FPConditionalCompareFixed = 0x1E200400,
1114  FPConditionalCompareFMask = 0x5F200C00,
1115  FPConditionalCompareMask = 0xFFE00C10,
1116  FCCMP_s = FPConditionalCompareFixed | 0x00000000,
1117  FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1118  FCCMP = FCCMP_s,
1119  FCCMPE_s = FPConditionalCompareFixed | 0x00000010,
1120  FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1121  FCCMPE = FCCMPE_s
1122 };
1123 
1124 // Floating point conditional select.
1125 enum FPConditionalSelectOp : uint32_t {
1126  FPConditionalSelectFixed = 0x1E200C00,
1127  FPConditionalSelectFMask = 0x5F200C00,
1128  FPConditionalSelectMask = 0xFFE00C00,
1129  FCSEL_s = FPConditionalSelectFixed | 0x00000000,
1130  FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1131  FCSEL = FCSEL_s
1132 };
1133 
1134 // Floating point immediate.
1135 enum FPImmediateOp : uint32_t {
1136  FPImmediateFixed = 0x1E201000,
1137  FPImmediateFMask = 0x5F201C00,
1138  FPImmediateMask = 0xFFE01C00,
1139  FMOV_s_imm = FPImmediateFixed | 0x00000000,
1140  FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1141 };
1142 
1143 // Floating point data processing 1 source.
1144 enum FPDataProcessing1SourceOp : uint32_t {
1145  FPDataProcessing1SourceFixed = 0x1E204000,
1146  FPDataProcessing1SourceFMask = 0x5F207C00,
1147  FPDataProcessing1SourceMask = 0xFFFFFC00,
1148  FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
1149  FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1150  FMOV = FMOV_s,
1151  FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
1152  FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1153  FABS = FABS_s,
1154  FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
1155  FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1156  FNEG = FNEG_s,
1157  FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
1158  FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1159  FSQRT = FSQRT_s,
1160  FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
1161  FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1162  FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000,
1163  FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
1164  FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000,
1165  FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000,
1166  FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1167  FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1168  FRINTN = FRINTN_s,
1169  FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1170  FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1171  FRINTP = FRINTP_s,
1172  FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1173  FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1174  FRINTM = FRINTM_s,
1175  FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1176  FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1177  FRINTZ = FRINTZ_s,
1178  FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1179  FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1180  FRINTA = FRINTA_s,
1181  FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1182  FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1183  FRINTX = FRINTX_s,
1184  FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1185  FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1186  FRINTI = FRINTI_s
1187 };
1188 
1189 // Floating point data processing 2 source.
1190 enum FPDataProcessing2SourceOp : uint32_t {
1191  FPDataProcessing2SourceFixed = 0x1E200800,
1192  FPDataProcessing2SourceFMask = 0x5F200C00,
1193  FPDataProcessing2SourceMask = 0xFFE0FC00,
1194  FMUL = FPDataProcessing2SourceFixed | 0x00000000,
1195  FMUL_s = FMUL,
1196  FMUL_d = FMUL | FP64,
1197  FDIV = FPDataProcessing2SourceFixed | 0x00001000,
1198  FDIV_s = FDIV,
1199  FDIV_d = FDIV | FP64,
1200  FADD = FPDataProcessing2SourceFixed | 0x00002000,
1201  FADD_s = FADD,
1202  FADD_d = FADD | FP64,
1203  FSUB = FPDataProcessing2SourceFixed | 0x00003000,
1204  FSUB_s = FSUB,
1205  FSUB_d = FSUB | FP64,
1206  FMAX = FPDataProcessing2SourceFixed | 0x00004000,
1207  FMAX_s = FMAX,
1208  FMAX_d = FMAX | FP64,
1209  FMIN = FPDataProcessing2SourceFixed | 0x00005000,
1210  FMIN_s = FMIN,
1211  FMIN_d = FMIN | FP64,
1212  FMAXNM = FPDataProcessing2SourceFixed | 0x00006000,
1213  FMAXNM_s = FMAXNM,
1214  FMAXNM_d = FMAXNM | FP64,
1215  FMINNM = FPDataProcessing2SourceFixed | 0x00007000,
1216  FMINNM_s = FMINNM,
1217  FMINNM_d = FMINNM | FP64,
1218  FNMUL = FPDataProcessing2SourceFixed | 0x00008000,
1219  FNMUL_s = FNMUL,
1220  FNMUL_d = FNMUL | FP64
1221 };
1222 
1223 // Floating point data processing 3 source.
1224 enum FPDataProcessing3SourceOp : uint32_t {
1225  FPDataProcessing3SourceFixed = 0x1F000000,
1226  FPDataProcessing3SourceFMask = 0x5F000000,
1227  FPDataProcessing3SourceMask = 0xFFE08000,
1228  FMADD_s = FPDataProcessing3SourceFixed | 0x00000000,
1229  FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000,
1230  FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000,
1231  FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000,
1232  FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
1233  FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000,
1234  FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000,
1235  FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
1236 };
1237 
1238 // Conversion between floating point and integer.
1239 enum FPIntegerConvertOp : uint32_t {
1240  FPIntegerConvertFixed = 0x1E200000,
1241  FPIntegerConvertFMask = 0x5F20FC00,
1242  FPIntegerConvertMask = 0xFFFFFC00,
1243  FCVTNS = FPIntegerConvertFixed | 0x00000000,
1244  FCVTNS_ws = FCVTNS,
1245  FCVTNS_xs = FCVTNS | SixtyFourBits,
1246  FCVTNS_wd = FCVTNS | FP64,
1247  FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1248  FCVTNU = FPIntegerConvertFixed | 0x00010000,
1249  FCVTNU_ws = FCVTNU,
1250  FCVTNU_xs = FCVTNU | SixtyFourBits,
1251  FCVTNU_wd = FCVTNU | FP64,
1252  FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1253  FCVTPS = FPIntegerConvertFixed | 0x00080000,
1254  FCVTPS_ws = FCVTPS,
1255  FCVTPS_xs = FCVTPS | SixtyFourBits,
1256  FCVTPS_wd = FCVTPS | FP64,
1257  FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1258  FCVTPU = FPIntegerConvertFixed | 0x00090000,
1259  FCVTPU_ws = FCVTPU,
1260  FCVTPU_xs = FCVTPU | SixtyFourBits,
1261  FCVTPU_wd = FCVTPU | FP64,
1262  FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1263  FCVTMS = FPIntegerConvertFixed | 0x00100000,
1264  FCVTMS_ws = FCVTMS,
1265  FCVTMS_xs = FCVTMS | SixtyFourBits,
1266  FCVTMS_wd = FCVTMS | FP64,
1267  FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1268  FCVTMU = FPIntegerConvertFixed | 0x00110000,
1269  FCVTMU_ws = FCVTMU,
1270  FCVTMU_xs = FCVTMU | SixtyFourBits,
1271  FCVTMU_wd = FCVTMU | FP64,
1272  FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1273  FCVTZS = FPIntegerConvertFixed | 0x00180000,
1274  FCVTZS_ws = FCVTZS,
1275  FCVTZS_xs = FCVTZS | SixtyFourBits,
1276  FCVTZS_wd = FCVTZS | FP64,
1277  FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1278  FCVTZU = FPIntegerConvertFixed | 0x00190000,
1279  FCVTZU_ws = FCVTZU,
1280  FCVTZU_xs = FCVTZU | SixtyFourBits,
1281  FCVTZU_wd = FCVTZU | FP64,
1282  FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1283  SCVTF = FPIntegerConvertFixed | 0x00020000,
1284  SCVTF_sw = SCVTF,
1285  SCVTF_sx = SCVTF | SixtyFourBits,
1286  SCVTF_dw = SCVTF | FP64,
1287  SCVTF_dx = SCVTF | SixtyFourBits | FP64,
1288  UCVTF = FPIntegerConvertFixed | 0x00030000,
1289  UCVTF_sw = UCVTF,
1290  UCVTF_sx = UCVTF | SixtyFourBits,
1291  UCVTF_dw = UCVTF | FP64,
1292  UCVTF_dx = UCVTF | SixtyFourBits | FP64,
1293  FCVTAS = FPIntegerConvertFixed | 0x00040000,
1294  FCVTAS_ws = FCVTAS,
1295  FCVTAS_xs = FCVTAS | SixtyFourBits,
1296  FCVTAS_wd = FCVTAS | FP64,
1297  FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1298  FCVTAU = FPIntegerConvertFixed | 0x00050000,
1299  FCVTAU_ws = FCVTAU,
1300  FCVTAU_xs = FCVTAU | SixtyFourBits,
1301  FCVTAU_wd = FCVTAU | FP64,
1302  FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1303  FMOV_ws = FPIntegerConvertFixed | 0x00060000,
1304  FMOV_sw = FPIntegerConvertFixed | 0x00070000,
1305  FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
1306  FMOV_dx = FMOV_sw | SixtyFourBits | FP64,
1307  FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
1308  FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000
1309 };
1310 
1311 // Conversion between fixed point and floating point.
1312 enum FPFixedPointConvertOp : uint32_t {
1313  FPFixedPointConvertFixed = 0x1E000000,
1314  FPFixedPointConvertFMask = 0x5F200000,
1315  FPFixedPointConvertMask = 0xFFFF0000,
1316  FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
1317  FCVTZS_ws_fixed = FCVTZS_fixed,
1318  FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1319  FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1320  FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1321  FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000,
1322  FCVTZU_ws_fixed = FCVTZU_fixed,
1323  FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1324  FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1325  FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1326  SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000,
1327  SCVTF_sw_fixed = SCVTF_fixed,
1328  SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
1329  SCVTF_dw_fixed = SCVTF_fixed | FP64,
1330  SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64,
1331  UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000,
1332  UCVTF_sw_fixed = UCVTF_fixed,
1333  UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits,
1334  UCVTF_dw_fixed = UCVTF_fixed | FP64,
1335  UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
1336 };
1337 
1338 // NEON instructions with two register operands.
1339 enum NEON2RegMiscOp : uint32_t {
1340  NEON2RegMiscFixed = 0x0E200800,
1341  NEON2RegMiscFMask = 0x9F3E0C00,
1342  NEON2RegMiscMask = 0xBF3FFC00,
1343  NEON2RegMiscUBit = 0x20000000,
1344  NEON_REV64 = NEON2RegMiscFixed | 0x00000000,
1345  NEON_REV32 = NEON2RegMiscFixed | 0x20000000,
1346  NEON_REV16 = NEON2RegMiscFixed | 0x00001000,
1347  NEON_SADDLP = NEON2RegMiscFixed | 0x00002000,
1348  NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit,
1349  NEON_SUQADD = NEON2RegMiscFixed | 0x00003000,
1350  NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit,
1351  NEON_CLS = NEON2RegMiscFixed | 0x00004000,
1352  NEON_CLZ = NEON2RegMiscFixed | 0x20004000,
1353  NEON_CNT = NEON2RegMiscFixed | 0x00005000,
1354  NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000,
1355  NEON_SADALP = NEON2RegMiscFixed | 0x00006000,
1356  NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit,
1357  NEON_SQABS = NEON2RegMiscFixed | 0x00007000,
1358  NEON_SQNEG = NEON2RegMiscFixed | 0x20007000,
1359  NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
1360  NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
1361  NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
1362  NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
1363  NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
1364  NEON_ABS = NEON2RegMiscFixed | 0x0000B000,
1365  NEON_NEG = NEON2RegMiscFixed | 0x2000B000,
1366  NEON_XTN = NEON2RegMiscFixed | 0x00012000,
1367  NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000,
1368  NEON_SHLL = NEON2RegMiscFixed | 0x20013000,
1369  NEON_SQXTN = NEON2RegMiscFixed | 0x00014000,
1370  NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit,
1371 
1372  NEON2RegMiscOpcode = 0x0001F000,
1373  NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
1374  NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
1375  NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
1376  NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
1377 
1378  // These instructions use only one bit of the size field. The other bit is
1379  // used to distinguish between instructions.
1380  NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
1381  NEON_FABS = NEON2RegMiscFixed | 0x0080F000,
1382  NEON_FNEG = NEON2RegMiscFixed | 0x2080F000,
1383  NEON_FCVTN = NEON2RegMiscFixed | 0x00016000,
1384  NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
1385  NEON_FCVTL = NEON2RegMiscFixed | 0x00017000,
1386  NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
1387  NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
1388  NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
1389  NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
1390  NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
1391  NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
1392  NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
1393  NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
1394  NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
1395  NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
1396  NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
1397  NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
1398  NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
1399  NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
1400  NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
1401  NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
1402  NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
1403  NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000,
1404  NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000,
1405  NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit,
1406  NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
1407  NEON_URECPE = NEON2RegMiscFixed | 0x0081C000,
1408  NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
1409  NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000,
1410  NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
1411  NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
1412  NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
1413  NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
1414  NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
1415 
1416  NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
1417  NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
1418 };
1419 
1420 // NEON instructions with three same-type operands.
1421 enum NEON3SameOp : uint32_t {
1422  NEON3SameFixed = 0x0E200400,
1423  NEON3SameFMask = 0x9F200400,
1424  NEON3SameMask = 0xBF20FC00,
1425  NEON3SameUBit = 0x20000000,
1426  NEON_ADD = NEON3SameFixed | 0x00008000,
1427  NEON_ADDP = NEON3SameFixed | 0x0000B800,
1428  NEON_SHADD = NEON3SameFixed | 0x00000000,
1429  NEON_SHSUB = NEON3SameFixed | 0x00002000,
1430  NEON_SRHADD = NEON3SameFixed | 0x00001000,
1431  NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800,
1432  NEON_CMGE = NEON3SameFixed | 0x00003800,
1433  NEON_CMGT = NEON3SameFixed | 0x00003000,
1434  NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
1435  NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
1436  NEON_CMTST = NEON3SameFixed | 0x00008800,
1437  NEON_MLA = NEON3SameFixed | 0x00009000,
1438  NEON_MLS = NEON3SameFixed | 0x20009000,
1439  NEON_MUL = NEON3SameFixed | 0x00009800,
1440  NEON_PMUL = NEON3SameFixed | 0x20009800,
1441  NEON_SRSHL = NEON3SameFixed | 0x00005000,
1442  NEON_SQSHL = NEON3SameFixed | 0x00004800,
1443  NEON_SQRSHL = NEON3SameFixed | 0x00005800,
1444  NEON_SSHL = NEON3SameFixed | 0x00004000,
1445  NEON_SMAX = NEON3SameFixed | 0x00006000,
1446  NEON_SMAXP = NEON3SameFixed | 0x0000A000,
1447  NEON_SMIN = NEON3SameFixed | 0x00006800,
1448  NEON_SMINP = NEON3SameFixed | 0x0000A800,
1449  NEON_SABD = NEON3SameFixed | 0x00007000,
1450  NEON_SABA = NEON3SameFixed | 0x00007800,
1451  NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
1452  NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
1453  NEON_SQADD = NEON3SameFixed | 0x00000800,
1454  NEON_SQSUB = NEON3SameFixed | 0x00002800,
1455  NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000,
1456  NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
1457  NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
1458  NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
1459  NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
1460  NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
1461  NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
1462  NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
1463  NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
1464  NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
1465  NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
1466  NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
1467  NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
1468  NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
1469  NEON_SQDMULH = NEON3SameFixed | 0x0000B000,
1470  NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
1471 
1472  // NEON floating point instructions with three same-type operands.
1473  NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
1474  NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
1475  NEON3SameFPMask = NEON3SameMask | 0x00800000,
1476  NEON_FADD = NEON3SameFixed | 0x0000D000,
1477  NEON_FSUB = NEON3SameFixed | 0x0080D000,
1478  NEON_FMUL = NEON3SameFixed | 0x2000D800,
1479  NEON_FDIV = NEON3SameFixed | 0x2000F800,
1480  NEON_FMAX = NEON3SameFixed | 0x0000F000,
1481  NEON_FMAXNM = NEON3SameFixed | 0x0000C000,
1482  NEON_FMAXP = NEON3SameFixed | 0x2000F000,
1483  NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
1484  NEON_FMIN = NEON3SameFixed | 0x0080F000,
1485  NEON_FMINNM = NEON3SameFixed | 0x0080C000,
1486  NEON_FMINP = NEON3SameFixed | 0x2080F000,
1487  NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
1488  NEON_FMLA = NEON3SameFixed | 0x0000C800,
1489  NEON_FMLS = NEON3SameFixed | 0x0080C800,
1490  NEON_FMULX = NEON3SameFixed | 0x0000D800,
1491  NEON_FRECPS = NEON3SameFixed | 0x0000F800,
1492  NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
1493  NEON_FABD = NEON3SameFixed | 0x2080D000,
1494  NEON_FADDP = NEON3SameFixed | 0x2000D000,
1495  NEON_FCMEQ = NEON3SameFixed | 0x0000E000,
1496  NEON_FCMGE = NEON3SameFixed | 0x2000E000,
1497  NEON_FCMGT = NEON3SameFixed | 0x2080E000,
1498  NEON_FACGE = NEON3SameFixed | 0x2000E800,
1499  NEON_FACGT = NEON3SameFixed | 0x2080E800,
1500 
1501  // NEON logical instructions with three same-type operands.
1502  NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
1503  NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
1504  NEON3SameLogicalMask = 0xBFE0FC00,
1505  NEON3SameLogicalFormatMask = NEON_Q,
1506  NEON_AND = NEON3SameLogicalFixed | 0x00000000,
1507  NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
1508  NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
1509  NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
1510  NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
1511  NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
1512  NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
1513  NEON_BSL = NEON3SameLogicalFixed | 0x20400000
1514 };
1515 
1516 // NEON instructions with three different-type operands.
1517 enum NEON3DifferentOp : uint32_t {
1518  NEON3DifferentFixed = 0x0E200000,
1519  NEON3DifferentFMask = 0x9F200C00,
1520  NEON3DifferentMask = 0xFF20FC00,
1521  NEON_ADDHN = NEON3DifferentFixed | 0x00004000,
1522  NEON_ADDHN2 = NEON_ADDHN | NEON_Q,
1523  NEON_PMULL = NEON3DifferentFixed | 0x0000E000,
1524  NEON_PMULL2 = NEON_PMULL | NEON_Q,
1525  NEON_RADDHN = NEON3DifferentFixed | 0x20004000,
1526  NEON_RADDHN2 = NEON_RADDHN | NEON_Q,
1527  NEON_RSUBHN = NEON3DifferentFixed | 0x20006000,
1528  NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q,
1529  NEON_SABAL = NEON3DifferentFixed | 0x00005000,
1530  NEON_SABAL2 = NEON_SABAL | NEON_Q,
1531  NEON_SABDL = NEON3DifferentFixed | 0x00007000,
1532  NEON_SABDL2 = NEON_SABDL | NEON_Q,
1533  NEON_SADDL = NEON3DifferentFixed | 0x00000000,
1534  NEON_SADDL2 = NEON_SADDL | NEON_Q,
1535  NEON_SADDW = NEON3DifferentFixed | 0x00001000,
1536  NEON_SADDW2 = NEON_SADDW | NEON_Q,
1537  NEON_SMLAL = NEON3DifferentFixed | 0x00008000,
1538  NEON_SMLAL2 = NEON_SMLAL | NEON_Q,
1539  NEON_SMLSL = NEON3DifferentFixed | 0x0000A000,
1540  NEON_SMLSL2 = NEON_SMLSL | NEON_Q,
1541  NEON_SMULL = NEON3DifferentFixed | 0x0000C000,
1542  NEON_SMULL2 = NEON_SMULL | NEON_Q,
1543  NEON_SSUBL = NEON3DifferentFixed | 0x00002000,
1544  NEON_SSUBL2 = NEON_SSUBL | NEON_Q,
1545  NEON_SSUBW = NEON3DifferentFixed | 0x00003000,
1546  NEON_SSUBW2 = NEON_SSUBW | NEON_Q,
1547  NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000,
1548  NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
1549  NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000,
1550  NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
1551  NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000,
1552  NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
1553  NEON_SUBHN = NEON3DifferentFixed | 0x00006000,
1554  NEON_SUBHN2 = NEON_SUBHN | NEON_Q,
1555  NEON_UABAL = NEON_SABAL | NEON3SameUBit,
1556  NEON_UABAL2 = NEON_UABAL | NEON_Q,
1557  NEON_UABDL = NEON_SABDL | NEON3SameUBit,
1558  NEON_UABDL2 = NEON_UABDL | NEON_Q,
1559  NEON_UADDL = NEON_SADDL | NEON3SameUBit,
1560  NEON_UADDL2 = NEON_UADDL | NEON_Q,
1561  NEON_UADDW = NEON_SADDW | NEON3SameUBit,
1562  NEON_UADDW2 = NEON_UADDW | NEON_Q,
1563  NEON_UMLAL = NEON_SMLAL | NEON3SameUBit,
1564  NEON_UMLAL2 = NEON_UMLAL | NEON_Q,
1565  NEON_UMLSL = NEON_SMLSL | NEON3SameUBit,
1566  NEON_UMLSL2 = NEON_UMLSL | NEON_Q,
1567  NEON_UMULL = NEON_SMULL | NEON3SameUBit,
1568  NEON_UMULL2 = NEON_UMULL | NEON_Q,
1569  NEON_USUBL = NEON_SSUBL | NEON3SameUBit,
1570  NEON_USUBL2 = NEON_USUBL | NEON_Q,
1571  NEON_USUBW = NEON_SSUBW | NEON3SameUBit,
1572  NEON_USUBW2 = NEON_USUBW | NEON_Q
1573 };
1574 
1575 // NEON instructions operating across vectors.
1576 enum NEONAcrossLanesOp : uint32_t {
1577  NEONAcrossLanesFixed = 0x0E300800,
1578  NEONAcrossLanesFMask = 0x9F3E0C00,
1579  NEONAcrossLanesMask = 0xBF3FFC00,
1580  NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000,
1581  NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
1582  NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
1583  NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000,
1584  NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000,
1585  NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000,
1586  NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000,
1587 
1588  // NEON floating point across instructions.
1589  NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x0000C000,
1590  NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x0000C000,
1591  NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x00800000,
1592 
1593  NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000,
1594  NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000,
1595  NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
1596  NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
1597 };
1598 
1599 // NEON instructions with indexed element operand.
1600 enum NEONByIndexedElementOp : uint32_t {
1601  NEONByIndexedElementFixed = 0x0F000000,
1602  NEONByIndexedElementFMask = 0x9F000400,
1603  NEONByIndexedElementMask = 0xBF00F400,
1604  NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000,
1605  NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000,
1606  NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000,
1607  NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
1608  NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
1609  NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
1610  NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
1611  NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
1612  NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
1613  NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
1614  NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
1615  NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
1616  NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000,
1617  NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
1618 
1619  // Floating point instructions.
1620  NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
1621  NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
1622  NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000,
1623  NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000,
1624  NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000,
1625  NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000
1626 };
1627 
1628 // NEON modified immediate.
1629 enum NEONModifiedImmediateOp : uint32_t {
1630  NEONModifiedImmediateFixed = 0x0F000400,
1631  NEONModifiedImmediateFMask = 0x9FF80400,
1632  NEONModifiedImmediateOpBit = 0x20000000,
1633  NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
1634  NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
1635  NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000,
1636  NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000
1637 };
1638 
1639 // NEON extract.
1640 enum NEONExtractOp : uint32_t {
1641  NEONExtractFixed = 0x2E000000,
1642  NEONExtractFMask = 0xBF208400,
1643  NEONExtractMask = 0xBFE08400,
1644  NEON_EXT = NEONExtractFixed | 0x00000000
1645 };
1646 
1647 enum NEONLoadStoreMultiOp : uint32_t {
1648  NEONLoadStoreMultiL = 0x00400000,
1649  NEONLoadStoreMulti1_1v = 0x00007000,
1650  NEONLoadStoreMulti1_2v = 0x0000A000,
1651  NEONLoadStoreMulti1_3v = 0x00006000,
1652  NEONLoadStoreMulti1_4v = 0x00002000,
1653  NEONLoadStoreMulti2 = 0x00008000,
1654  NEONLoadStoreMulti3 = 0x00004000,
1655  NEONLoadStoreMulti4 = 0x00000000
1656 };
1657 
1658 // NEON load/store multiple structures.
1659 enum NEONLoadStoreMultiStructOp : uint32_t {
1660  NEONLoadStoreMultiStructFixed = 0x0C000000,
1661  NEONLoadStoreMultiStructFMask = 0xBFBF0000,
1662  NEONLoadStoreMultiStructMask = 0xBFFFF000,
1663  NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
1664  NEONLoadStoreMultiStructLoad =
1665  NEONLoadStoreMultiStructFixed | NEONLoadStoreMultiL,
1666  NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
1667  NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
1668  NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
1669  NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
1670  NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
1671  NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
1672  NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
1673  NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
1674  NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
1675  NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
1676  NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
1677  NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
1678  NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
1679  NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
1680 };
1681 
1682 // NEON load/store multiple structures with post-index addressing.
1683 enum NEONLoadStoreMultiStructPostIndexOp : uint32_t {
1684  NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
1685  NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
1686  NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000,
1687  NEONLoadStoreMultiStructPostIndex = 0x00800000,
1688  NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
1689  NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
1690  NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
1691  NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
1692  NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
1693  NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
1694  NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
1695  NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
1696  NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
1697  NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
1698  NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
1699  NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
1700  NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
1701  NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
1702 };
1703 
1704 enum NEONLoadStoreSingleOp : uint32_t {
1705  NEONLoadStoreSingle1 = 0x00000000,
1706  NEONLoadStoreSingle2 = 0x00200000,
1707  NEONLoadStoreSingle3 = 0x00002000,
1708  NEONLoadStoreSingle4 = 0x00202000,
1709  NEONLoadStoreSingleL = 0x00400000,
1710  NEONLoadStoreSingle_b = 0x00000000,
1711  NEONLoadStoreSingle_h = 0x00004000,
1712  NEONLoadStoreSingle_s = 0x00008000,
1713  NEONLoadStoreSingle_d = 0x00008400,
1714  NEONLoadStoreSingleAllLanes = 0x0000C000,
1715  NEONLoadStoreSingleLenMask = 0x00202000
1716 };
1717 
1718 // NEON load/store single structure.
1719 enum NEONLoadStoreSingleStructOp : uint32_t {
1720  NEONLoadStoreSingleStructFixed = 0x0D000000,
1721  NEONLoadStoreSingleStructFMask = 0xBF9F0000,
1722  NEONLoadStoreSingleStructMask = 0xBFFFE000,
1723  NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
1724  NEONLoadStoreSingleStructLoad =
1725  NEONLoadStoreSingleStructFixed | NEONLoadStoreSingleL,
1726  NEONLoadStoreSingleStructLoad1 =
1727  NEONLoadStoreSingle1 | NEONLoadStoreSingleStructLoad,
1728  NEONLoadStoreSingleStructLoad2 =
1729  NEONLoadStoreSingle2 | NEONLoadStoreSingleStructLoad,
1730  NEONLoadStoreSingleStructLoad3 =
1731  NEONLoadStoreSingle3 | NEONLoadStoreSingleStructLoad,
1732  NEONLoadStoreSingleStructLoad4 =
1733  NEONLoadStoreSingle4 | NEONLoadStoreSingleStructLoad,
1734  NEONLoadStoreSingleStructStore1 =
1735  NEONLoadStoreSingle1 | NEONLoadStoreSingleStructFixed,
1736  NEONLoadStoreSingleStructStore2 =
1737  NEONLoadStoreSingle2 | NEONLoadStoreSingleStructFixed,
1738  NEONLoadStoreSingleStructStore3 =
1739  NEONLoadStoreSingle3 | NEONLoadStoreSingleStructFixed,
1740  NEONLoadStoreSingleStructStore4 =
1741  NEONLoadStoreSingle4 | NEONLoadStoreSingleStructFixed,
1742  NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
1743  NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
1744  NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
1745  NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
1746  NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
1747  NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
1748  NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
1749  NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
1750  NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
1751 
1752  NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
1753  NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
1754  NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
1755  NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
1756  NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
1757  NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
1758  NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
1759  NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
1760  NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
1761 
1762  NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
1763  NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
1764  NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
1765  NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
1766  NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
1767  NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
1768  NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
1769  NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
1770  NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
1771 
1772  NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
1773  NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
1774  NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
1775  NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
1776  NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
1777  NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
1778  NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
1779  NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
1780  NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
1781 };
1782 
1783 // NEON load/store single structure with post-index addressing.
1784 enum NEONLoadStoreSingleStructPostIndexOp : uint32_t {
1785  NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
1786  NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
1787  NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000,
1788  NEONLoadStoreSingleStructPostIndex = 0x00800000,
1789  NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
1790  NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
1791  NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
1792  NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
1793  NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
1794  NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
1795  NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
1796  NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
1797  NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
1798 
1799  NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
1800  NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
1801  NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
1802  NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
1803  NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
1804  NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
1805  NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
1806  NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
1807  NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
1808 
1809  NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
1810  NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
1811  NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
1812  NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
1813  NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
1814  NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
1815  NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
1816  NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
1817  NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
1818 
1819  NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
1820  NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
1821  NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
1822  NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
1823  NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
1824  NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
1825  NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
1826  NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
1827  NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
1828 };
1829 
1830 // NEON register copy.
1831 enum NEONCopyOp : uint32_t {
1832  NEONCopyFixed = 0x0E000400,
1833  NEONCopyFMask = 0x9FE08400,
1834  NEONCopyMask = 0x3FE08400,
1835  NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
1836  NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
1837  NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
1838  NEONCopyDupGeneralMask = NEONCopyDupElementMask,
1839  NEONCopyUmovMask = NEONCopyMask | 0x20007800,
1840  NEONCopySmovMask = NEONCopyMask | 0x20007800,
1841  NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000,
1842  NEON_INS_GENERAL = NEONCopyFixed | 0x40001800,
1843  NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000,
1844  NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800,
1845  NEON_SMOV = NEONCopyFixed | 0x00002800,
1846  NEON_UMOV = NEONCopyFixed | 0x00003800
1847 };
1848 
1849 // NEON scalar instructions with indexed element operand.
1850 enum NEONScalarByIndexedElementOp : uint32_t {
1851  NEONScalarByIndexedElementFixed = 0x5F000000,
1852  NEONScalarByIndexedElementFMask = 0xDF000400,
1853  NEONScalarByIndexedElementMask = 0xFF00F400,
1854  NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
1855  NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
1856  NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
1857  NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
1858  NEON_SQRDMULH_byelement_scalar =
1859  NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
1860 
1861  // Floating point instructions.
1862  NEONScalarByIndexedElementFPFixed =
1863  NEONScalarByIndexedElementFixed | 0x00800000,
1864  NEONScalarByIndexedElementFPMask =
1865  NEONScalarByIndexedElementMask | 0x00800000,
1866  NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement,
1867  NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement,
1868  NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement,
1869  NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
1870 };
1871 
1872 // NEON shift immediate.
1873 enum NEONShiftImmediateOp : uint32_t {
1874  NEONShiftImmediateFixed = 0x0F000400,
1875  NEONShiftImmediateFMask = 0x9F800400,
1876  NEONShiftImmediateMask = 0xBF80FC00,
1877  NEONShiftImmediateUBit = 0x20000000,
1878  NEON_SHL = NEONShiftImmediateFixed | 0x00005000,
1879  NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000,
1880  NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000,
1881  NEON_SLI = NEONShiftImmediateFixed | 0x20005000,
1882  NEON_SRI = NEONShiftImmediateFixed | 0x20004000,
1883  NEON_SHRN = NEONShiftImmediateFixed | 0x00008000,
1884  NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800,
1885  NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000,
1886  NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800,
1887  NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000,
1888  NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800,
1889  NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000,
1890  NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
1891  NEON_SSHR = NEONShiftImmediateFixed | 0x00000000,
1892  NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000,
1893  NEON_USHR = NEONShiftImmediateFixed | 0x20000000,
1894  NEON_URSHR = NEONShiftImmediateFixed | 0x20002000,
1895  NEON_SSRA = NEONShiftImmediateFixed | 0x00001000,
1896  NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000,
1897  NEON_USRA = NEONShiftImmediateFixed | 0x20001000,
1898  NEON_URSRA = NEONShiftImmediateFixed | 0x20003000,
1899  NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000,
1900  NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
1901  NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
1902  NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
1903  NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
1904  NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
1905  NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
1906 };
1907 
1908 // NEON scalar register copy.
1909 enum NEONScalarCopyOp : uint32_t {
1910  NEONScalarCopyFixed = 0x5E000400,
1911  NEONScalarCopyFMask = 0xDFE08400,
1912  NEONScalarCopyMask = 0xFFE0FC00,
1913  NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
1914 };
1915 
1916 // NEON scalar pairwise instructions.
1917 enum NEONScalarPairwiseOp : uint32_t {
1918  NEONScalarPairwiseFixed = 0x5E300800,
1919  NEONScalarPairwiseFMask = 0xDF3E0C00,
1920  NEONScalarPairwiseMask = 0xFFB1F800,
1921  NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000,
1922  NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000,
1923  NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000,
1924  NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000,
1925  NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000,
1926  NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000
1927 };
1928 
1929 // NEON scalar shift immediate.
1930 enum NEONScalarShiftImmediateOp : uint32_t {
1931  NEONScalarShiftImmediateFixed = 0x5F000400,
1932  NEONScalarShiftImmediateFMask = 0xDF800400,
1933  NEONScalarShiftImmediateMask = 0xFF80FC00,
1934  NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL,
1935  NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI,
1936  NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI,
1937  NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
1938  NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
1939  NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
1940  NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
1941  NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
1942  NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
1943  NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
1944  NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
1945  NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
1946  NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
1947  NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
1948  NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
1949  NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
1950  NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
1951  NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
1952  NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm,
1953  NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm,
1954  NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
1955  NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
1956  NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
1957  NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
1958 };
1959 
1960 // NEON table.
1961 enum NEONTableOp : uint32_t {
1962  NEONTableFixed = 0x0E000000,
1963  NEONTableFMask = 0xBF208C00,
1964  NEONTableExt = 0x00001000,
1965  NEONTableMask = 0xBF20FC00,
1966  NEON_TBL_1v = NEONTableFixed | 0x00000000,
1967  NEON_TBL_2v = NEONTableFixed | 0x00002000,
1968  NEON_TBL_3v = NEONTableFixed | 0x00004000,
1969  NEON_TBL_4v = NEONTableFixed | 0x00006000,
1970  NEON_TBX_1v = NEON_TBL_1v | NEONTableExt,
1971  NEON_TBX_2v = NEON_TBL_2v | NEONTableExt,
1972  NEON_TBX_3v = NEON_TBL_3v | NEONTableExt,
1973  NEON_TBX_4v = NEON_TBL_4v | NEONTableExt
1974 };
1975 
1976 // NEON perm.
1977 enum NEONPermOp : uint32_t {
1978  NEONPermFixed = 0x0E000800,
1979  NEONPermFMask = 0xBF208C00,
1980  NEONPermMask = 0x3F20FC00,
1981  NEON_UZP1 = NEONPermFixed | 0x00001000,
1982  NEON_TRN1 = NEONPermFixed | 0x00002000,
1983  NEON_ZIP1 = NEONPermFixed | 0x00003000,
1984  NEON_UZP2 = NEONPermFixed | 0x00005000,
1985  NEON_TRN2 = NEONPermFixed | 0x00006000,
1986  NEON_ZIP2 = NEONPermFixed | 0x00007000
1987 };
1988 
1989 // NEON scalar instructions with two register operands.
1990 enum NEONScalar2RegMiscOp : uint32_t {
1991  NEONScalar2RegMiscFixed = 0x5E200800,
1992  NEONScalar2RegMiscFMask = 0xDF3E0C00,
1993  NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
1994  NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
1995  NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
1996  NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
1997  NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
1998  NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
1999  NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS,
2000  NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS,
2001  NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG,
2002  NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG,
2003  NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN,
2004  NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN,
2005  NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN,
2006  NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD,
2007  NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD,
2008 
2009  NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
2010  NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
2011 
2012  NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000,
2013  NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE,
2014  NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE,
2015  NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF,
2016  NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF,
2017  NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
2018  NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
2019  NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
2020  NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
2021  NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
2022  NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000,
2023  NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS,
2024  NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU,
2025  NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS,
2026  NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU,
2027  NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS,
2028  NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU,
2029  NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS,
2030  NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU,
2031  NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS,
2032  NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU,
2033  NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN
2034 };
2035 
2036 // NEON scalar instructions with three same-type operands.
2037 enum NEONScalar3SameOp : uint32_t {
2038  NEONScalar3SameFixed = 0x5E200400,
2039  NEONScalar3SameFMask = 0xDF200400,
2040  NEONScalar3SameMask = 0xFF20FC00,
2041  NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD,
2042  NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ,
2043  NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE,
2044  NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT,
2045  NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI,
2046  NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS,
2047  NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST,
2048  NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB,
2049  NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD,
2050  NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD,
2051  NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB,
2052  NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB,
2053  NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL,
2054  NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL,
2055  NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL,
2056  NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL,
2057  NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL,
2058  NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL,
2059  NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
2060  NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
2061  NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
2062  NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
2063 
2064  // NEON floating point scalar instructions with three same-type operands.
2065  NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
2066  NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
2067  NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000,
2068  NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE,
2069  NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT,
2070  NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ,
2071  NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE,
2072  NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT,
2073  NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX,
2074  NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS,
2075  NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
2076  NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD
2077 };
2078 
2079 // NEON scalar instructions with three different-type operands.
2080 enum NEONScalar3DiffOp : uint32_t {
2081  NEONScalar3DiffFixed = 0x5E200000,
2082  NEONScalar3DiffFMask = 0xDF200C00,
2083  NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask,
2084  NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL,
2085  NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL,
2086  NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL
2087 };
2088 
2089 // Unimplemented and unallocated instructions. These are defined to make fixed
2090 // bit assertion easier.
2091 enum UnimplementedOp : uint32_t {
2092  UnimplementedFixed = 0x00000000,
2093  UnimplementedFMask = 0x00000000
2094 };
2095 
2096 enum UnallocatedOp : uint32_t {
2097  UnallocatedFixed = 0x00000000,
2098  UnallocatedFMask = 0x00000000
2099 };
2100 
2101 } // namespace internal
2102 } // namespace v8
2103 
2104 #endif // V8_ARM64_CONSTANTS_ARM64_H_
int64_t
v8
Definition: libplatform.h:13
uint32_t