V8 API Reference, 7.2.502.16 (for Deno 0.2.4)
codegen-mips.cc
1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #if V8_TARGET_ARCH_MIPS
6 
7 #include <memory>
8 
9 #include "src/codegen.h"
10 #include "src/macro-assembler.h"
11 #include "src/mips/simulator-mips.h"
12 
13 namespace v8 {
14 namespace internal {
15 
16 #define __ masm.
17 
18 #if defined(V8_HOST_ARCH_MIPS)
19 
20 MemCopyUint8Function CreateMemCopyUint8Function(MemCopyUint8Function stub) {
21 #if defined(USE_SIMULATOR) || defined(_MIPS_ARCH_MIPS32R6) || \
22  defined(_MIPS_ARCH_MIPS32RX)
23  return stub;
24 #else
25  v8::PageAllocator* page_allocator = GetPlatformPageAllocator();
26  size_t allocated = 0;
27  byte* buffer = AllocatePage(page_allocator,
28  page_allocator->GetRandomMmapAddr(), &allocated);
29  if (buffer == nullptr) return nullptr;
30 
31  MacroAssembler masm(AssemblerOptions{}, buffer, static_cast<int>(allocated));
32 
33  // This code assumes that cache lines are 32 bytes and if the cache line is
34  // larger it will not work correctly.
35  {
36  Label lastb, unaligned, aligned, chkw,
37  loop16w, chk1w, wordCopy_loop, skip_pref, lastbloop,
38  leave, ua_chk16w, ua_loop16w, ua_skip_pref, ua_chkw,
39  ua_chk1w, ua_wordCopy_loop, ua_smallCopy, ua_smallCopy_loop;
40 
41  // The size of each prefetch.
42  uint32_t pref_chunk = 32;
43  // The maximum size of a prefetch, it must not be less than pref_chunk.
44  // If the real size of a prefetch is greater than max_pref_size and
45  // the kPrefHintPrepareForStore hint is used, the code will not work
46  // correctly.
47  uint32_t max_pref_size = 128;
48  DCHECK(pref_chunk < max_pref_size);
49 
50  // pref_limit is set based on the fact that we never use an offset
51  // greater then 5 on a store pref and that a single pref can
52  // never be larger then max_pref_size.
53  uint32_t pref_limit = (5 * pref_chunk) + max_pref_size;
54  int32_t pref_hint_load = kPrefHintLoadStreamed;
55  int32_t pref_hint_store = kPrefHintPrepareForStore;
56  uint32_t loadstore_chunk = 4;
57 
58  // The initial prefetches may fetch bytes that are before the buffer being
59  // copied. Start copies with an offset of 4 so avoid this situation when
60  // using kPrefHintPrepareForStore.
61  DCHECK(pref_hint_store != kPrefHintPrepareForStore ||
62  pref_chunk * 4 >= max_pref_size);
63 
64  // If the size is less than 8, go to lastb. Regardless of size,
65  // copy dst pointer to v0 for the retuen value.
66  __ slti(t2, a2, 2 * loadstore_chunk);
67  __ bne(t2, zero_reg, &lastb);
68  __ mov(v0, a0); // In delay slot.
69 
70  // If src and dst have different alignments, go to unaligned, if they
71  // have the same alignment (but are not actually aligned) do a partial
72  // load/store to make them aligned. If they are both already aligned
73  // we can start copying at aligned.
74  __ xor_(t8, a1, a0);
75  __ andi(t8, t8, loadstore_chunk - 1); // t8 is a0/a1 word-displacement.
76  __ bne(t8, zero_reg, &unaligned);
77  __ subu(a3, zero_reg, a0); // In delay slot.
78 
79  __ andi(a3, a3, loadstore_chunk - 1); // Copy a3 bytes to align a0/a1.
80  __ beq(a3, zero_reg, &aligned); // Already aligned.
81  __ subu(a2, a2, a3); // In delay slot. a2 is the remining bytes count.
82 
83  if (kArchEndian == kLittle) {
84  __ lwr(t8, MemOperand(a1));
85  __ addu(a1, a1, a3);
86  __ swr(t8, MemOperand(a0));
87  __ addu(a0, a0, a3);
88  } else {
89  __ lwl(t8, MemOperand(a1));
90  __ addu(a1, a1, a3);
91  __ swl(t8, MemOperand(a0));
92  __ addu(a0, a0, a3);
93  }
94  // Now dst/src are both aligned to (word) aligned addresses. Set a2 to
95  // count how many bytes we have to copy after all the 64 byte chunks are
96  // copied and a3 to the dst pointer after all the 64 byte chunks have been
97  // copied. We will loop, incrementing a0 and a1 until a0 equals a3.
98  __ bind(&aligned);
99  __ andi(t8, a2, 0x3F);
100  __ beq(a2, t8, &chkw); // Less than 64?
101  __ subu(a3, a2, t8); // In delay slot.
102  __ addu(a3, a0, a3); // Now a3 is the final dst after loop.
103 
104  // When in the loop we prefetch with kPrefHintPrepareForStore hint,
105  // in this case the a0+x should be past the "t0-32" address. This means:
106  // for x=128 the last "safe" a0 address is "t0-160". Alternatively, for
107  // x=64 the last "safe" a0 address is "t0-96". In the current version we
108  // will use "pref hint, 128(a0)", so "t0-160" is the limit.
109  if (pref_hint_store == kPrefHintPrepareForStore) {
110  __ addu(t0, a0, a2); // t0 is the "past the end" address.
111  __ Subu(t9, t0, pref_limit); // t9 is the "last safe pref" address.
112  }
113 
114  __ Pref(pref_hint_load, MemOperand(a1, 0 * pref_chunk));
115  __ Pref(pref_hint_load, MemOperand(a1, 1 * pref_chunk));
116  __ Pref(pref_hint_load, MemOperand(a1, 2 * pref_chunk));
117  __ Pref(pref_hint_load, MemOperand(a1, 3 * pref_chunk));
118 
119  if (pref_hint_store != kPrefHintPrepareForStore) {
120  __ Pref(pref_hint_store, MemOperand(a0, 1 * pref_chunk));
121  __ Pref(pref_hint_store, MemOperand(a0, 2 * pref_chunk));
122  __ Pref(pref_hint_store, MemOperand(a0, 3 * pref_chunk));
123  }
124  __ bind(&loop16w);
125  __ lw(t0, MemOperand(a1));
126 
127  if (pref_hint_store == kPrefHintPrepareForStore) {
128  __ sltu(v1, t9, a0); // If a0 > t9, don't use next prefetch.
129  __ Branch(USE_DELAY_SLOT, &skip_pref, gt, v1, Operand(zero_reg));
130  }
131  __ lw(t1, MemOperand(a1, 1, loadstore_chunk)); // Maybe in delay slot.
132 
133  __ Pref(pref_hint_store, MemOperand(a0, 4 * pref_chunk));
134  __ Pref(pref_hint_store, MemOperand(a0, 5 * pref_chunk));
135 
136  __ bind(&skip_pref);
137  __ lw(t2, MemOperand(a1, 2, loadstore_chunk));
138  __ lw(t3, MemOperand(a1, 3, loadstore_chunk));
139  __ lw(t4, MemOperand(a1, 4, loadstore_chunk));
140  __ lw(t5, MemOperand(a1, 5, loadstore_chunk));
141  __ lw(t6, MemOperand(a1, 6, loadstore_chunk));
142  __ lw(t7, MemOperand(a1, 7, loadstore_chunk));
143  __ Pref(pref_hint_load, MemOperand(a1, 4 * pref_chunk));
144 
145  __ sw(t0, MemOperand(a0));
146  __ sw(t1, MemOperand(a0, 1, loadstore_chunk));
147  __ sw(t2, MemOperand(a0, 2, loadstore_chunk));
148  __ sw(t3, MemOperand(a0, 3, loadstore_chunk));
149  __ sw(t4, MemOperand(a0, 4, loadstore_chunk));
150  __ sw(t5, MemOperand(a0, 5, loadstore_chunk));
151  __ sw(t6, MemOperand(a0, 6, loadstore_chunk));
152  __ sw(t7, MemOperand(a0, 7, loadstore_chunk));
153 
154  __ lw(t0, MemOperand(a1, 8, loadstore_chunk));
155  __ lw(t1, MemOperand(a1, 9, loadstore_chunk));
156  __ lw(t2, MemOperand(a1, 10, loadstore_chunk));
157  __ lw(t3, MemOperand(a1, 11, loadstore_chunk));
158  __ lw(t4, MemOperand(a1, 12, loadstore_chunk));
159  __ lw(t5, MemOperand(a1, 13, loadstore_chunk));
160  __ lw(t6, MemOperand(a1, 14, loadstore_chunk));
161  __ lw(t7, MemOperand(a1, 15, loadstore_chunk));
162  __ Pref(pref_hint_load, MemOperand(a1, 5 * pref_chunk));
163 
164  __ sw(t0, MemOperand(a0, 8, loadstore_chunk));
165  __ sw(t1, MemOperand(a0, 9, loadstore_chunk));
166  __ sw(t2, MemOperand(a0, 10, loadstore_chunk));
167  __ sw(t3, MemOperand(a0, 11, loadstore_chunk));
168  __ sw(t4, MemOperand(a0, 12, loadstore_chunk));
169  __ sw(t5, MemOperand(a0, 13, loadstore_chunk));
170  __ sw(t6, MemOperand(a0, 14, loadstore_chunk));
171  __ sw(t7, MemOperand(a0, 15, loadstore_chunk));
172  __ addiu(a0, a0, 16 * loadstore_chunk);
173  __ bne(a0, a3, &loop16w);
174  __ addiu(a1, a1, 16 * loadstore_chunk); // In delay slot.
175  __ mov(a2, t8);
176 
177  // Here we have src and dest word-aligned but less than 64-bytes to go.
178  // Check for a 32 bytes chunk and copy if there is one. Otherwise jump
179  // down to chk1w to handle the tail end of the copy.
180  __ bind(&chkw);
181  __ Pref(pref_hint_load, MemOperand(a1, 0 * pref_chunk));
182  __ andi(t8, a2, 0x1F);
183  __ beq(a2, t8, &chk1w); // Less than 32?
184  __ nop(); // In delay slot.
185  __ lw(t0, MemOperand(a1));
186  __ lw(t1, MemOperand(a1, 1, loadstore_chunk));
187  __ lw(t2, MemOperand(a1, 2, loadstore_chunk));
188  __ lw(t3, MemOperand(a1, 3, loadstore_chunk));
189  __ lw(t4, MemOperand(a1, 4, loadstore_chunk));
190  __ lw(t5, MemOperand(a1, 5, loadstore_chunk));
191  __ lw(t6, MemOperand(a1, 6, loadstore_chunk));
192  __ lw(t7, MemOperand(a1, 7, loadstore_chunk));
193  __ addiu(a1, a1, 8 * loadstore_chunk);
194  __ sw(t0, MemOperand(a0));
195  __ sw(t1, MemOperand(a0, 1, loadstore_chunk));
196  __ sw(t2, MemOperand(a0, 2, loadstore_chunk));
197  __ sw(t3, MemOperand(a0, 3, loadstore_chunk));
198  __ sw(t4, MemOperand(a0, 4, loadstore_chunk));
199  __ sw(t5, MemOperand(a0, 5, loadstore_chunk));
200  __ sw(t6, MemOperand(a0, 6, loadstore_chunk));
201  __ sw(t7, MemOperand(a0, 7, loadstore_chunk));
202  __ addiu(a0, a0, 8 * loadstore_chunk);
203 
204  // Here we have less than 32 bytes to copy. Set up for a loop to copy
205  // one word at a time. Set a2 to count how many bytes we have to copy
206  // after all the word chunks are copied and a3 to the dst pointer after
207  // all the word chunks have been copied. We will loop, incrementing a0
208  // and a1 until a0 equals a3.
209  __ bind(&chk1w);
210  __ andi(a2, t8, loadstore_chunk - 1);
211  __ beq(a2, t8, &lastb);
212  __ subu(a3, t8, a2); // In delay slot.
213  __ addu(a3, a0, a3);
214 
215  __ bind(&wordCopy_loop);
216  __ lw(t3, MemOperand(a1));
217  __ addiu(a0, a0, loadstore_chunk);
218  __ addiu(a1, a1, loadstore_chunk);
219  __ bne(a0, a3, &wordCopy_loop);
220  __ sw(t3, MemOperand(a0, -1, loadstore_chunk)); // In delay slot.
221 
222  __ bind(&lastb);
223  __ Branch(&leave, le, a2, Operand(zero_reg));
224  __ addu(a3, a0, a2);
225 
226  __ bind(&lastbloop);
227  __ lb(v1, MemOperand(a1));
228  __ addiu(a0, a0, 1);
229  __ addiu(a1, a1, 1);
230  __ bne(a0, a3, &lastbloop);
231  __ sb(v1, MemOperand(a0, -1)); // In delay slot.
232 
233  __ bind(&leave);
234  __ jr(ra);
235  __ nop();
236 
237  // Unaligned case. Only the dst gets aligned so we need to do partial
238  // loads of the source followed by normal stores to the dst (once we
239  // have aligned the destination).
240  __ bind(&unaligned);
241  __ andi(a3, a3, loadstore_chunk - 1); // Copy a3 bytes to align a0/a1.
242  __ beq(a3, zero_reg, &ua_chk16w);
243  __ subu(a2, a2, a3); // In delay slot.
244 
245  if (kArchEndian == kLittle) {
246  __ lwr(v1, MemOperand(a1));
247  __ lwl(v1,
248  MemOperand(a1, 1, loadstore_chunk, MemOperand::offset_minus_one));
249  __ addu(a1, a1, a3);
250  __ swr(v1, MemOperand(a0));
251  __ addu(a0, a0, a3);
252  } else {
253  __ lwl(v1, MemOperand(a1));
254  __ lwr(v1,
255  MemOperand(a1, 1, loadstore_chunk, MemOperand::offset_minus_one));
256  __ addu(a1, a1, a3);
257  __ swl(v1, MemOperand(a0));
258  __ addu(a0, a0, a3);
259  }
260 
261  // Now the dst (but not the source) is aligned. Set a2 to count how many
262  // bytes we have to copy after all the 64 byte chunks are copied and a3 to
263  // the dst pointer after all the 64 byte chunks have been copied. We will
264  // loop, incrementing a0 and a1 until a0 equals a3.
265  __ bind(&ua_chk16w);
266  __ andi(t8, a2, 0x3F);
267  __ beq(a2, t8, &ua_chkw);
268  __ subu(a3, a2, t8); // In delay slot.
269  __ addu(a3, a0, a3);
270 
271  if (pref_hint_store == kPrefHintPrepareForStore) {
272  __ addu(t0, a0, a2);
273  __ Subu(t9, t0, pref_limit);
274  }
275 
276  __ Pref(pref_hint_load, MemOperand(a1, 0 * pref_chunk));
277  __ Pref(pref_hint_load, MemOperand(a1, 1 * pref_chunk));
278  __ Pref(pref_hint_load, MemOperand(a1, 2 * pref_chunk));
279 
280  if (pref_hint_store != kPrefHintPrepareForStore) {
281  __ Pref(pref_hint_store, MemOperand(a0, 1 * pref_chunk));
282  __ Pref(pref_hint_store, MemOperand(a0, 2 * pref_chunk));
283  __ Pref(pref_hint_store, MemOperand(a0, 3 * pref_chunk));
284  }
285 
286  __ bind(&ua_loop16w);
287  __ Pref(pref_hint_load, MemOperand(a1, 3 * pref_chunk));
288  if (kArchEndian == kLittle) {
289  __ lwr(t0, MemOperand(a1));
290  __ lwr(t1, MemOperand(a1, 1, loadstore_chunk));
291  __ lwr(t2, MemOperand(a1, 2, loadstore_chunk));
292 
293  if (pref_hint_store == kPrefHintPrepareForStore) {
294  __ sltu(v1, t9, a0);
295  __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg));
296  }
297  __ lwr(t3, MemOperand(a1, 3, loadstore_chunk)); // Maybe in delay slot.
298 
299  __ Pref(pref_hint_store, MemOperand(a0, 4 * pref_chunk));
300  __ Pref(pref_hint_store, MemOperand(a0, 5 * pref_chunk));
301 
302  __ bind(&ua_skip_pref);
303  __ lwr(t4, MemOperand(a1, 4, loadstore_chunk));
304  __ lwr(t5, MemOperand(a1, 5, loadstore_chunk));
305  __ lwr(t6, MemOperand(a1, 6, loadstore_chunk));
306  __ lwr(t7, MemOperand(a1, 7, loadstore_chunk));
307  __ lwl(t0,
308  MemOperand(a1, 1, loadstore_chunk, MemOperand::offset_minus_one));
309  __ lwl(t1,
310  MemOperand(a1, 2, loadstore_chunk, MemOperand::offset_minus_one));
311  __ lwl(t2,
312  MemOperand(a1, 3, loadstore_chunk, MemOperand::offset_minus_one));
313  __ lwl(t3,
314  MemOperand(a1, 4, loadstore_chunk, MemOperand::offset_minus_one));
315  __ lwl(t4,
316  MemOperand(a1, 5, loadstore_chunk, MemOperand::offset_minus_one));
317  __ lwl(t5,
318  MemOperand(a1, 6, loadstore_chunk, MemOperand::offset_minus_one));
319  __ lwl(t6,
320  MemOperand(a1, 7, loadstore_chunk, MemOperand::offset_minus_one));
321  __ lwl(t7,
322  MemOperand(a1, 8, loadstore_chunk, MemOperand::offset_minus_one));
323  } else {
324  __ lwl(t0, MemOperand(a1));
325  __ lwl(t1, MemOperand(a1, 1, loadstore_chunk));
326  __ lwl(t2, MemOperand(a1, 2, loadstore_chunk));
327 
328  if (pref_hint_store == kPrefHintPrepareForStore) {
329  __ sltu(v1, t9, a0);
330  __ Branch(USE_DELAY_SLOT, &ua_skip_pref, gt, v1, Operand(zero_reg));
331  }
332  __ lwl(t3, MemOperand(a1, 3, loadstore_chunk)); // Maybe in delay slot.
333 
334  __ Pref(pref_hint_store, MemOperand(a0, 4 * pref_chunk));
335  __ Pref(pref_hint_store, MemOperand(a0, 5 * pref_chunk));
336 
337  __ bind(&ua_skip_pref);
338  __ lwl(t4, MemOperand(a1, 4, loadstore_chunk));
339  __ lwl(t5, MemOperand(a1, 5, loadstore_chunk));
340  __ lwl(t6, MemOperand(a1, 6, loadstore_chunk));
341  __ lwl(t7, MemOperand(a1, 7, loadstore_chunk));
342  __ lwr(t0,
343  MemOperand(a1, 1, loadstore_chunk, MemOperand::offset_minus_one));
344  __ lwr(t1,
345  MemOperand(a1, 2, loadstore_chunk, MemOperand::offset_minus_one));
346  __ lwr(t2,
347  MemOperand(a1, 3, loadstore_chunk, MemOperand::offset_minus_one));
348  __ lwr(t3,
349  MemOperand(a1, 4, loadstore_chunk, MemOperand::offset_minus_one));
350  __ lwr(t4,
351  MemOperand(a1, 5, loadstore_chunk, MemOperand::offset_minus_one));
352  __ lwr(t5,
353  MemOperand(a1, 6, loadstore_chunk, MemOperand::offset_minus_one));
354  __ lwr(t6,
355  MemOperand(a1, 7, loadstore_chunk, MemOperand::offset_minus_one));
356  __ lwr(t7,
357  MemOperand(a1, 8, loadstore_chunk, MemOperand::offset_minus_one));
358  }
359  __ Pref(pref_hint_load, MemOperand(a1, 4 * pref_chunk));
360  __ sw(t0, MemOperand(a0));
361  __ sw(t1, MemOperand(a0, 1, loadstore_chunk));
362  __ sw(t2, MemOperand(a0, 2, loadstore_chunk));
363  __ sw(t3, MemOperand(a0, 3, loadstore_chunk));
364  __ sw(t4, MemOperand(a0, 4, loadstore_chunk));
365  __ sw(t5, MemOperand(a0, 5, loadstore_chunk));
366  __ sw(t6, MemOperand(a0, 6, loadstore_chunk));
367  __ sw(t7, MemOperand(a0, 7, loadstore_chunk));
368  if (kArchEndian == kLittle) {
369  __ lwr(t0, MemOperand(a1, 8, loadstore_chunk));
370  __ lwr(t1, MemOperand(a1, 9, loadstore_chunk));
371  __ lwr(t2, MemOperand(a1, 10, loadstore_chunk));
372  __ lwr(t3, MemOperand(a1, 11, loadstore_chunk));
373  __ lwr(t4, MemOperand(a1, 12, loadstore_chunk));
374  __ lwr(t5, MemOperand(a1, 13, loadstore_chunk));
375  __ lwr(t6, MemOperand(a1, 14, loadstore_chunk));
376  __ lwr(t7, MemOperand(a1, 15, loadstore_chunk));
377  __ lwl(t0,
378  MemOperand(a1, 9, loadstore_chunk, MemOperand::offset_minus_one));
379  __ lwl(t1,
380  MemOperand(a1, 10, loadstore_chunk, MemOperand::offset_minus_one));
381  __ lwl(t2,
382  MemOperand(a1, 11, loadstore_chunk, MemOperand::offset_minus_one));
383  __ lwl(t3,
384  MemOperand(a1, 12, loadstore_chunk, MemOperand::offset_minus_one));
385  __ lwl(t4,
386  MemOperand(a1, 13, loadstore_chunk, MemOperand::offset_minus_one));
387  __ lwl(t5,
388  MemOperand(a1, 14, loadstore_chunk, MemOperand::offset_minus_one));
389  __ lwl(t6,
390  MemOperand(a1, 15, loadstore_chunk, MemOperand::offset_minus_one));
391  __ lwl(t7,
392  MemOperand(a1, 16, loadstore_chunk, MemOperand::offset_minus_one));
393  } else {
394  __ lwl(t0, MemOperand(a1, 8, loadstore_chunk));
395  __ lwl(t1, MemOperand(a1, 9, loadstore_chunk));
396  __ lwl(t2, MemOperand(a1, 10, loadstore_chunk));
397  __ lwl(t3, MemOperand(a1, 11, loadstore_chunk));
398  __ lwl(t4, MemOperand(a1, 12, loadstore_chunk));
399  __ lwl(t5, MemOperand(a1, 13, loadstore_chunk));
400  __ lwl(t6, MemOperand(a1, 14, loadstore_chunk));
401  __ lwl(t7, MemOperand(a1, 15, loadstore_chunk));
402  __ lwr(t0,
403  MemOperand(a1, 9, loadstore_chunk, MemOperand::offset_minus_one));
404  __ lwr(t1,
405  MemOperand(a1, 10, loadstore_chunk, MemOperand::offset_minus_one));
406  __ lwr(t2,
407  MemOperand(a1, 11, loadstore_chunk, MemOperand::offset_minus_one));
408  __ lwr(t3,
409  MemOperand(a1, 12, loadstore_chunk, MemOperand::offset_minus_one));
410  __ lwr(t4,
411  MemOperand(a1, 13, loadstore_chunk, MemOperand::offset_minus_one));
412  __ lwr(t5,
413  MemOperand(a1, 14, loadstore_chunk, MemOperand::offset_minus_one));
414  __ lwr(t6,
415  MemOperand(a1, 15, loadstore_chunk, MemOperand::offset_minus_one));
416  __ lwr(t7,
417  MemOperand(a1, 16, loadstore_chunk, MemOperand::offset_minus_one));
418  }
419  __ Pref(pref_hint_load, MemOperand(a1, 5 * pref_chunk));
420  __ sw(t0, MemOperand(a0, 8, loadstore_chunk));
421  __ sw(t1, MemOperand(a0, 9, loadstore_chunk));
422  __ sw(t2, MemOperand(a0, 10, loadstore_chunk));
423  __ sw(t3, MemOperand(a0, 11, loadstore_chunk));
424  __ sw(t4, MemOperand(a0, 12, loadstore_chunk));
425  __ sw(t5, MemOperand(a0, 13, loadstore_chunk));
426  __ sw(t6, MemOperand(a0, 14, loadstore_chunk));
427  __ sw(t7, MemOperand(a0, 15, loadstore_chunk));
428  __ addiu(a0, a0, 16 * loadstore_chunk);
429  __ bne(a0, a3, &ua_loop16w);
430  __ addiu(a1, a1, 16 * loadstore_chunk); // In delay slot.
431  __ mov(a2, t8);
432 
433  // Here less than 64-bytes. Check for
434  // a 32 byte chunk and copy if there is one. Otherwise jump down to
435  // ua_chk1w to handle the tail end of the copy.
436  __ bind(&ua_chkw);
437  __ Pref(pref_hint_load, MemOperand(a1));
438  __ andi(t8, a2, 0x1F);
439 
440  __ beq(a2, t8, &ua_chk1w);
441  __ nop(); // In delay slot.
442  if (kArchEndian == kLittle) {
443  __ lwr(t0, MemOperand(a1));
444  __ lwr(t1, MemOperand(a1, 1, loadstore_chunk));
445  __ lwr(t2, MemOperand(a1, 2, loadstore_chunk));
446  __ lwr(t3, MemOperand(a1, 3, loadstore_chunk));
447  __ lwr(t4, MemOperand(a1, 4, loadstore_chunk));
448  __ lwr(t5, MemOperand(a1, 5, loadstore_chunk));
449  __ lwr(t6, MemOperand(a1, 6, loadstore_chunk));
450  __ lwr(t7, MemOperand(a1, 7, loadstore_chunk));
451  __ lwl(t0,
452  MemOperand(a1, 1, loadstore_chunk, MemOperand::offset_minus_one));
453  __ lwl(t1,
454  MemOperand(a1, 2, loadstore_chunk, MemOperand::offset_minus_one));
455  __ lwl(t2,
456  MemOperand(a1, 3, loadstore_chunk, MemOperand::offset_minus_one));
457  __ lwl(t3,
458  MemOperand(a1, 4, loadstore_chunk, MemOperand::offset_minus_one));
459  __ lwl(t4,
460  MemOperand(a1, 5, loadstore_chunk, MemOperand::offset_minus_one));
461  __ lwl(t5,
462  MemOperand(a1, 6, loadstore_chunk, MemOperand::offset_minus_one));
463  __ lwl(t6,
464  MemOperand(a1, 7, loadstore_chunk, MemOperand::offset_minus_one));
465  __ lwl(t7,
466  MemOperand(a1, 8, loadstore_chunk, MemOperand::offset_minus_one));
467  } else {
468  __ lwl(t0, MemOperand(a1));
469  __ lwl(t1, MemOperand(a1, 1, loadstore_chunk));
470  __ lwl(t2, MemOperand(a1, 2, loadstore_chunk));
471  __ lwl(t3, MemOperand(a1, 3, loadstore_chunk));
472  __ lwl(t4, MemOperand(a1, 4, loadstore_chunk));
473  __ lwl(t5, MemOperand(a1, 5, loadstore_chunk));
474  __ lwl(t6, MemOperand(a1, 6, loadstore_chunk));
475  __ lwl(t7, MemOperand(a1, 7, loadstore_chunk));
476  __ lwr(t0,
477  MemOperand(a1, 1, loadstore_chunk, MemOperand::offset_minus_one));
478  __ lwr(t1,
479  MemOperand(a1, 2, loadstore_chunk, MemOperand::offset_minus_one));
480  __ lwr(t2,
481  MemOperand(a1, 3, loadstore_chunk, MemOperand::offset_minus_one));
482  __ lwr(t3,
483  MemOperand(a1, 4, loadstore_chunk, MemOperand::offset_minus_one));
484  __ lwr(t4,
485  MemOperand(a1, 5, loadstore_chunk, MemOperand::offset_minus_one));
486  __ lwr(t5,
487  MemOperand(a1, 6, loadstore_chunk, MemOperand::offset_minus_one));
488  __ lwr(t6,
489  MemOperand(a1, 7, loadstore_chunk, MemOperand::offset_minus_one));
490  __ lwr(t7,
491  MemOperand(a1, 8, loadstore_chunk, MemOperand::offset_minus_one));
492  }
493  __ addiu(a1, a1, 8 * loadstore_chunk);
494  __ sw(t0, MemOperand(a0));
495  __ sw(t1, MemOperand(a0, 1, loadstore_chunk));
496  __ sw(t2, MemOperand(a0, 2, loadstore_chunk));
497  __ sw(t3, MemOperand(a0, 3, loadstore_chunk));
498  __ sw(t4, MemOperand(a0, 4, loadstore_chunk));
499  __ sw(t5, MemOperand(a0, 5, loadstore_chunk));
500  __ sw(t6, MemOperand(a0, 6, loadstore_chunk));
501  __ sw(t7, MemOperand(a0, 7, loadstore_chunk));
502  __ addiu(a0, a0, 8 * loadstore_chunk);
503 
504  // Less than 32 bytes to copy. Set up for a loop to
505  // copy one word at a time.
506  __ bind(&ua_chk1w);
507  __ andi(a2, t8, loadstore_chunk - 1);
508  __ beq(a2, t8, &ua_smallCopy);
509  __ subu(a3, t8, a2); // In delay slot.
510  __ addu(a3, a0, a3);
511 
512  __ bind(&ua_wordCopy_loop);
513  if (kArchEndian == kLittle) {
514  __ lwr(v1, MemOperand(a1));
515  __ lwl(v1,
516  MemOperand(a1, 1, loadstore_chunk, MemOperand::offset_minus_one));
517  } else {
518  __ lwl(v1, MemOperand(a1));
519  __ lwr(v1,
520  MemOperand(a1, 1, loadstore_chunk, MemOperand::offset_minus_one));
521  }
522  __ addiu(a0, a0, loadstore_chunk);
523  __ addiu(a1, a1, loadstore_chunk);
524  __ bne(a0, a3, &ua_wordCopy_loop);
525  __ sw(v1, MemOperand(a0, -1, loadstore_chunk)); // In delay slot.
526 
527  // Copy the last 8 bytes.
528  __ bind(&ua_smallCopy);
529  __ beq(a2, zero_reg, &leave);
530  __ addu(a3, a0, a2); // In delay slot.
531 
532  __ bind(&ua_smallCopy_loop);
533  __ lb(v1, MemOperand(a1));
534  __ addiu(a0, a0, 1);
535  __ addiu(a1, a1, 1);
536  __ bne(a0, a3, &ua_smallCopy_loop);
537  __ sb(v1, MemOperand(a0, -1)); // In delay slot.
538 
539  __ jr(ra);
540  __ nop();
541  }
542  CodeDesc desc;
543  masm.GetCode(nullptr, &desc);
544  DCHECK(!RelocInfo::RequiresRelocationAfterCodegen(desc));
545 
546  Assembler::FlushICache(buffer, allocated);
547  CHECK(SetPermissions(page_allocator, buffer, allocated,
548  PageAllocator::kReadExecute));
549  return FUNCTION_CAST<MemCopyUint8Function>(buffer);
550 #endif
551 }
552 #endif
553 
554 UnaryMathFunction CreateSqrtFunction() {
555 #if defined(USE_SIMULATOR)
556  return nullptr;
557 #else
558  v8::PageAllocator* page_allocator = GetPlatformPageAllocator();
559  size_t allocated = 0;
560  byte* buffer = AllocatePage(page_allocator,
561  page_allocator->GetRandomMmapAddr(), &allocated);
562  if (buffer == nullptr) return nullptr;
563 
564  MacroAssembler masm(AssemblerOptions{}, buffer, static_cast<int>(allocated));
565 
566  __ MovFromFloatParameter(f12);
567  __ sqrt_d(f0, f12);
568  __ MovToFloatResult(f0);
569  __ Ret();
570 
571  CodeDesc desc;
572  masm.GetCode(nullptr, &desc);
573  DCHECK(!RelocInfo::RequiresRelocationAfterCodegen(desc));
574 
575  Assembler::FlushICache(buffer, allocated);
576  CHECK(SetPermissions(page_allocator, buffer, allocated,
577  PageAllocator::kReadExecute));
578  return FUNCTION_CAST<UnaryMathFunction>(buffer);
579 #endif
580 }
581 
582 #undef __
583 
584 } // namespace internal
585 } // namespace v8
586 
587 #endif // V8_TARGET_ARCH_MIPS
v8::PageAllocator::GetRandomMmapAddr
virtual void * GetRandomMmapAddr()=0
v8
Definition: libplatform.h:13
uint32_t